From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54961) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZtcL4-0001fT-0f for qemu-devel@nongnu.org; Tue, 03 Nov 2015 09:13:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZtcL3-0007um-3n for qemu-devel@nongnu.org; Tue, 03 Nov 2015 09:13:29 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35243) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZtcL2-0007sB-Ss for qemu-devel@nongnu.org; Tue, 03 Nov 2015 09:13:29 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZtcKt-0003FP-MD for qemu-devel@nongnu.org; Tue, 03 Nov 2015 14:13:19 +0000 From: Peter Maydell Date: Tue, 3 Nov 2015 14:13:15 +0000 Message-Id: <1446559999-12413-10-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1446559999-12413-1-git-send-email-peter.maydell@linaro.org> References: <1446559999-12413-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 09/13] target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The AArch64 debug CPU display of PSTATE as "PSTATE=200003c5 (flags --C-)" on the end of the same line as the last of the general purpose registers is unnecessarily different from the AArch32 display of PSR as "PSR=200001d3 --C- A svc32" on its own line. Update the AArch64 code to put PSTATE in its own line and in the same format, including printing the exception level (mode). Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Alex Bennée Message-id: 1445883178-576-2-git-send-email-peter.maydell@linaro.org --- target-arm/translate-a64.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 83b8376..57503a0 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -126,6 +126,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, CPUARMState *env = &cpu->env; uint32_t psr = pstate_read(env); int i; + int el = arm_current_el(env); cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", env->pc, env->xregs[31]); @@ -137,13 +138,14 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, " "); } } - cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", + cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', psr & PSTATE_C ? 'C' : '-', - psr & PSTATE_V ? 'V' : '-'); - cpu_fprintf(f, "\n"); + psr & PSTATE_V ? 'V' : '-', + el, + psr & PSTATE_SP ? 'h' : 't'); if (flags & CPU_DUMP_FPU) { int numvfpregs = 32; -- 1.9.1