From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55957) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zthiv-0003Og-OE for qemu-devel@nongnu.org; Tue, 03 Nov 2015 14:58:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zthiu-0001y9-VT for qemu-devel@nongnu.org; Tue, 03 Nov 2015 14:58:29 -0500 Received: from mx1.redhat.com ([209.132.183.28]:45055) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zthiu-0001xp-Ps for qemu-devel@nongnu.org; Tue, 03 Nov 2015 14:58:28 -0500 From: Eduardo Habkost Date: Tue, 3 Nov 2015 17:58:14 -0200 Message-Id: <1446580695-28525-3-git-send-email-ehabkost@redhat.com> In-Reply-To: <1446580695-28525-1-git-send-email-ehabkost@redhat.com> References: <1446580695-28525-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [PATCH v2 2/3] target-i386: Remove SSE4a from qemu64 CPU model List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Igor Mammedov , Richard Henderson , "Dr. David Alan Gilbert" , "Michael S. Tsirkin" SSE4a is not available in any Intel CPU, and we want to make the default CPU runnable in most hosts, so it doesn't make sense to enable it by default in KVM mode. We should eventually have all features supported by TCG enabled by default in TCG mode, but as we don't have a good mechanism today to ensure we have different defaults in KVM and TCG mode, disable SSE4a in the qemu64 CPU model entirely. Signed-off-by: Eduardo Habkost --- include/hw/i386/pc.h | 5 +++++ target-i386/cpu.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 8be4520..bc82c14 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -327,6 +327,11 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); .driver = TYPE_X86_CPU,\ .property = "check",\ .value = "off",\ + },\ + {\ + .driver = "qemu64" "-" TYPE_X86_CPU,\ + .property = "sse4a",\ + .value = "on",\ }, #define PC_COMPAT_2_3 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 9280bfc..f270ddb 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -676,7 +676,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | - CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, + CPUID_EXT3_ABM, .xlevel = 0x8000000A, }, { -- 2.1.0