From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50162) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zu5Uw-0006Ac-HX for qemu-devel@nongnu.org; Wed, 04 Nov 2015 16:21:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zu5Ur-00068N-Jd for qemu-devel@nongnu.org; Wed, 04 Nov 2015 16:21:38 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zu5Ur-00068J-Cc for qemu-devel@nongnu.org; Wed, 04 Nov 2015 16:21:33 -0500 From: Eduardo Habkost Date: Wed, 4 Nov 2015 19:21:19 -0200 Message-Id: <1446672079-8549-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [kvm-unit-test RFC] x86: Memory instructions test case List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Xiao Guangrong , kvm@vger.kernel.org, Richard Henderson Quickly hacked test case for memory instructions (clflush, mfence, sfence, lfence, clflushopt, clwb, pcommit), that simply checks for #UD exceptions. This was useful to test TCG handling of those instructions. The "fake clwb" part will probably break once a new instruction use those opcodes. Signed-off-by: Eduardo Habkost --- config/config-x86-common.mak | 2 + config/config-x86_64.mak | 2 +- x86/memory.c | 88 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 x86/memory.c diff --git a/config/config-x86-common.mak b/config/config-x86-common.mak index c2f9908..b89684d 100644 --- a/config/config-x86-common.mak +++ b/config/config-x86-common.mak @@ -108,6 +108,8 @@ $(TEST_DIR)/vmx.elf: $(cstart.o) $(TEST_DIR)/vmx.o $(TEST_DIR)/vmx_tests.o $(TEST_DIR)/debug.elf: $(cstart.o) $(TEST_DIR)/debug.o +$(TEST_DIR)/memory.elf: $(cstart.o) $(TEST_DIR)/memory.o + arch_clean: $(RM) $(TEST_DIR)/*.o $(TEST_DIR)/*.flat $(TEST_DIR)/*.elf \ $(TEST_DIR)/.*.d lib/x86/.*.d diff --git a/config/config-x86_64.mak b/config/config-x86_64.mak index 7d4eb34..ec4bded 100644 --- a/config/config-x86_64.mak +++ b/config/config-x86_64.mak @@ -7,7 +7,7 @@ tests = $(TEST_DIR)/access.flat $(TEST_DIR)/apic.flat \ $(TEST_DIR)/emulator.flat $(TEST_DIR)/idt_test.flat \ $(TEST_DIR)/xsave.flat $(TEST_DIR)/rmap_chain.flat \ $(TEST_DIR)/pcid.flat $(TEST_DIR)/debug.flat \ - $(TEST_DIR)/ioapic.flat + $(TEST_DIR)/ioapic.flat $(TEST_DIR)/memory.flat tests += $(TEST_DIR)/svm.flat tests += $(TEST_DIR)/vmx.flat tests += $(TEST_DIR)/tscdeadline_latency.flat diff --git a/x86/memory.c b/x86/memory.c new file mode 100644 index 0000000..cd1eb46 --- /dev/null +++ b/x86/memory.c @@ -0,0 +1,88 @@ +/* + * Test for x86 cache and memory instructions + * + * Copyright (c) 2015 Red Hat Inc + * + * Authors: + * Eduardo Habkost + * + * This work is licensed under the terms of the GNU GPL, version 2. + */ + +#include "libcflat.h" +#include "desc.h" +#include "processor.h" + +static long target; +static volatile int ud; +static volatile int isize; + +static void handle_ud(struct ex_regs *regs) +{ + ud = 1; + regs->rip += isize; +} + +int main(int ac, char **av) +{ + struct cpuid cpuid7, cpuid1; + int xfail; + + setup_idt(); + handle_exception(UD_VECTOR, handle_ud); + + cpuid1 = cpuid(1); + cpuid7 = cpuid_indexed(7, 0); + + /* 3-byte instructions: */ + isize = 3; + + xfail = !(cpuid1.d & (1U << 19)); /* CLFLUSH */ + ud = 0; + asm volatile("clflush (%0)" : : "b" (&target)); + report_xfail("clflush", xfail, ud == 0); + + xfail = !(cpuid1.d & (1U << 25)); /* SSE */ + ud = 0; + asm volatile("sfence"); + report_xfail("sfence", xfail, ud == 0); + + xfail = !(cpuid1.d & (1U << 26)); /* SSE2 */ + ud = 0; + asm volatile("lfence"); + report_xfail("lfence", xfail, ud == 0); + + ud = 0; + asm volatile("mfence"); + report_xfail("mfence", xfail, ud == 0); + + /* 4-byte instructions: */ + isize = 4; + + xfail = !(cpuid7.b & (1U << 23)); /* CLFLUSHOPT */ + ud = 0; + /* clflushopt (%rbx): */ + asm volatile(".byte 0x66, 0x0f, 0xae, 0x3b" : : "b" (&target)); + report_xfail("clflushopt", xfail, ud == 0); + + xfail = !(cpuid7.b & (1U << 24)); /* CLWB */ + ud = 0; + /* clwb (%rbx): */ + asm volatile(".byte 0x66, 0x0f, 0xae, 0x33" : : "b" (&target)); + report_xfail("clwb", xfail, ud == 0); + + ud = 0; + /* clwb requires a memory operand, the following is NOT a valid + * CLWB instruction (modrm == 0xF0). + */ + asm volatile(".byte 0x66, 0x0f, 0xae, 0xf0"); + report("fake clwb", ud); + + xfail = !(cpuid7.b & (1U << 22)); /* PCOMMIT */ + ud = 0; + /* pcommit: */ + asm volatile(".byte 0x66, 0x0f, 0xae, 0xf8"); + report_xfail("pcommit", xfail, ud == 0); + + return report_summary(); +} -- 2.1.0