From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: patches@linaro.org, qemu-arm@nongnu.org,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [PATCH 16/16] HACK: rearrange the virt memory map to suit OP-TEE
Date: Thu, 5 Nov 2015 18:15:58 +0000 [thread overview]
Message-ID: <1446747358-18214-17-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1446747358-18214-1-git-send-email-peter.maydell@linaro.org>
The current OP-TEE codebase expects the secure UART to
be at 0x09010000 and irq 2 (it is based on an old
non-upstream patch to add a second uart, and upstream
used that memory map area for something else). When
the TZ support is upstream in QEMU we can move OP-TEE
on to a proper upstream QEMU and update it to use the
new UART location, but for now this hack patch allows
running a more-or-less unmodified OP-TEE.
Put the secure UART at the address and irq where OP-TEE
expects it, moving some other devices down to make space.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 162896f..a6b87ba 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -118,9 +118,9 @@ static const MemMapEntry a15memmap[] = {
/* This redistributor space allows up to 2*64kB*123 CPUs */
[VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
[VIRT_UART] = { 0x09000000, 0x00001000 },
- [VIRT_RTC] = { 0x09010000, 0x00001000 },
- [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
- [VIRT_SECURE_UART] = { 0x09030000, 0x00001000 },
+ [VIRT_RTC] = { 0x09020000, 0x00001000 },
+ [VIRT_FW_CFG] = { 0x09030000, 0x00000018 },
+ [VIRT_SECURE_UART] = { 0x09010000, 0x00001000 },
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
[VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
@@ -134,9 +134,9 @@ static const MemMapEntry a15memmap[] = {
static const int a15irqmap[] = {
[VIRT_UART] = 1,
- [VIRT_RTC] = 2,
- [VIRT_PCIE] = 3, /* ... to 6 */
- [VIRT_SECURE_UART] = 7,
+ [VIRT_RTC] = 3,
+ [VIRT_PCIE] = 4, /* ... to 7 */
+ [VIRT_SECURE_UART] = 2,
[VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
[VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
--
1.9.1
prev parent reply other threads:[~2015-11-05 18:16 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-05 18:15 [Qemu-devel] [PATCH 00/16] Add support for multiple address spaces per CPU and use it for ARM TrustZone Peter Maydell
2015-11-05 18:15 ` [Qemu-devel] [PATCH 01/16] exec.c: Don't set cpu->as until cpu_address_space_init Peter Maydell
2015-11-06 13:04 ` Edgar E. Iglesias
2015-11-05 18:15 ` [Qemu-devel] [PATCH 02/16] exec.c: Allow target CPUs to define multiple AddressSpaces Peter Maydell
2015-11-06 13:21 ` Edgar E. Iglesias
2015-11-06 13:34 ` Peter Maydell
2015-11-06 13:49 ` Edgar E. Iglesias
2015-11-09 10:32 ` Paolo Bonzini
2015-11-09 10:30 ` Paolo Bonzini
2015-11-05 18:15 ` [Qemu-devel] [PATCH 03/16] tlb_set_page_with_attrs: Take argument specifying AddressSpace to use Peter Maydell
2015-11-06 13:27 ` Edgar E. Iglesias
2015-11-06 13:41 ` Peter Maydell
2015-11-06 13:49 ` Edgar E. Iglesias
2015-11-06 13:52 ` Edgar E. Iglesias
2015-11-09 10:44 ` Paolo Bonzini
2015-11-09 10:49 ` Peter Maydell
2015-11-10 16:13 ` Peter Maydell
2015-11-05 18:15 ` [Qemu-devel] [PATCH 04/16] exec.c: Add address space index to CPUIOTLBEntry Peter Maydell
2015-11-06 13:34 ` Edgar E. Iglesias
2015-11-06 13:45 ` Peter Maydell
2015-11-06 14:13 ` Edgar E. Iglesias
2015-11-05 18:15 ` [Qemu-devel] [PATCH 05/16] exec.c: Add cpu_get_address_space() Peter Maydell
2015-11-05 18:15 ` [Qemu-devel] [PATCH 06/16] include/qom/cpu.h: Add new get_phys_page_asidx_debug method Peter Maydell
2015-11-06 13:37 ` Edgar E. Iglesias
2015-11-05 18:15 ` [Qemu-devel] [PATCH 07/16] exec.c: Use cpu_get_phys_page_asidx_debug Peter Maydell
2015-11-06 13:38 ` Edgar E. Iglesias
2015-11-05 18:15 ` [Qemu-devel] [PATCH 08/16] exec.c: Have one io_mem_watch per AddressSpace Peter Maydell
2015-11-06 13:45 ` Edgar E. Iglesias
2015-11-09 10:49 ` Paolo Bonzini
2015-11-09 10:54 ` Peter Maydell
2015-11-09 11:00 ` Paolo Bonzini
2015-11-05 18:15 ` [Qemu-devel] [PATCH 09/16] target-arm: Support multiple address spaces in page table walks Peter Maydell
2015-11-06 14:22 ` Edgar E. Iglesias
2015-11-09 10:51 ` Paolo Bonzini
2015-11-09 10:58 ` Peter Maydell
2015-11-09 11:03 ` Paolo Bonzini
2015-11-09 11:09 ` Peter Maydell
2015-11-09 11:19 ` Paolo Bonzini
2015-11-09 11:22 ` Peter Maydell
2015-11-13 18:51 ` Peter Maydell
2015-11-05 18:15 ` [Qemu-devel] [PATCH 10/16] target-arm: Implement cpu_get_phys_page_asidx_debug Peter Maydell
2015-11-06 14:23 ` Edgar E. Iglesias
2015-11-05 18:15 ` [Qemu-devel] [PATCH 11/16] memory: Add address_space_init_shareable() Peter Maydell
2015-11-06 14:29 ` Edgar E. Iglesias
2015-11-06 14:49 ` Peter Maydell
2015-11-09 10:55 ` Paolo Bonzini
2015-11-09 10:59 ` Peter Maydell
2015-11-09 11:02 ` Paolo Bonzini
2015-11-05 18:15 ` [Qemu-devel] [PATCH 12/16] qom/cpu: Add MemoryRegion property Peter Maydell
2015-11-06 14:31 ` Edgar E. Iglesias
2015-11-09 10:56 ` Paolo Bonzini
2015-11-05 18:15 ` [Qemu-devel] [PATCH 13/16] target-arm: Add QOM property for Secure memory region Peter Maydell
2015-11-06 14:33 ` Edgar E. Iglesias
2015-11-05 18:15 ` [Qemu-devel] [PATCH 14/16] hw/arm/virt: Wire up memory region to CPUs explicitly Peter Maydell
2015-11-06 14:45 ` Edgar E. Iglesias
2015-11-06 14:51 ` Peter Maydell
2015-11-05 18:15 ` [Qemu-devel] [PATCH 15/16] [RFC] hw/arm/virt: add secure memory region and UART Peter Maydell
2015-11-05 18:15 ` Peter Maydell [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1446747358-18214-17-git-send-email-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=afaerber@suse.de \
--cc=alex.bennee@linaro.org \
--cc=edgar.iglesias@gmail.com \
--cc=patches@linaro.org \
--cc=pbonzini@redhat.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).