From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43232) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZuQLp-0004xD-30 for qemu-devel@nongnu.org; Thu, 05 Nov 2015 14:37:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZuQLk-0005he-BB for qemu-devel@nongnu.org; Thu, 05 Nov 2015 14:37:37 -0500 Received: from mx1.redhat.com ([209.132.183.28]:33505) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZuQLk-0005hU-5g for qemu-devel@nongnu.org; Thu, 05 Nov 2015 14:37:32 -0500 From: Eduardo Habkost Date: Thu, 5 Nov 2015 17:37:11 -0200 Message-Id: <1446752231-3715-6-git-send-email-ehabkost@redhat.com> In-Reply-To: <1446752231-3715-1-git-send-email-ehabkost@redhat.com> References: <1446752231-3715-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [PULL 5/5] target-i386: Enable clflushopt/clwb/pcommit instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , Richard Henderson , Xiao Guangrong , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel@nongnu.org From: Xiao Guangrong These instructions are used by NVDIMM drivers and the specification is located at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf There instructions are available on Skylake Server. Signed-off-by: Xiao Guangrong Reviewed-by: Richard Henderson Signed-off-by: Eduardo Habkost --- target-i386/cpu.c | 4 ++-- target-i386/cpu.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 090d1d8..0d080c1 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -259,8 +259,8 @@ static const char *svm_feature_name[] = { static const char *cpuid_7_0_ebx_feature_name[] = { "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL, - "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL, - NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, + "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt", + "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, }; static const char *cpuid_apm_edx_feature_name[] = { diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 62f7879..fc4a605 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -576,6 +576,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_RDSEED (1U << 18) #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ +#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ +#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */ -- 2.1.0