From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60247) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZucAs-00023D-7S for qemu-devel@nongnu.org; Fri, 06 Nov 2015 03:15:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZucAn-0003Kx-7c for qemu-devel@nongnu.org; Fri, 06 Nov 2015 03:15:06 -0500 Received: from e23smtp02.au.ibm.com ([202.81.31.144]:51597) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZucAm-0003Hj-Ec for qemu-devel@nongnu.org; Fri, 06 Nov 2015 03:15:00 -0500 Received: from localhost by e23smtp02.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Fri, 6 Nov 2015 17:44:36 +1000 From: Bharata B Rao Date: Fri, 6 Nov 2015 13:12:59 +0530 Message-Id: <1446795779-28086-1-git-send-email-bharata@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH] ppc: Add/Re-introduce MMU model definitions needed by PR KVM List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aik@ozlabs.ru, qemu-ppc@nongnu.org, aneesh.kumar@linux.vnet.ibm.com, Bharata B Rao , david@gibson.dropbear.id.au Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) removed the mmu_model definition POWERPC_MMU_2_06a which is needed by PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting of PR KVM guest. Signed-off-by: Bharata B Rao Cc: Benjamin Herrenschmidt --- target-ppc/cpu.h | 6 ++++++ target-ppc/mmu_helper.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b34aed6..31c6fee 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -122,9 +122,15 @@ enum powerpc_mmu_t { /* Architecture 2.06 variant */ POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000003, + /* Architecture 2.06 "degraded" (no 1T segments) */ + POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000003, /* Architecture 2.07 variant */ POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_AMR | 0x00000004, + /* Architecture 2.07 "degraded" (no 1T segments) */ + POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR + | 0x00000004, #endif /* defined(TARGET_PPC64) */ }; diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index e52d0e5..30298d8 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1295,7 +1295,9 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: dump_slb(f, cpu_fprintf, env); break; #endif @@ -1435,7 +1437,9 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: return ppc_hash64_get_phys_page_debug(env, addr); #endif @@ -1939,7 +1943,9 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: #endif /* defined(TARGET_PPC64) */ tlb_flush(CPU(cpu), 1); break; @@ -2013,7 +2019,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_64B: case POWERPC_MMU_2_03: case POWERPC_MMU_2_06: + case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: + case POWERPC_MMU_2_07a: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, -- 2.1.0