From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zvb1R-0001M5-H2 for qemu-devel@nongnu.org; Sun, 08 Nov 2015 20:13:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zvb1P-0007yX-Uc for qemu-devel@nongnu.org; Sun, 08 Nov 2015 20:13:25 -0500 From: Michael Davidsaver Date: Sun, 8 Nov 2015 20:11:39 -0500 Message-Id: <1447031505-12477-13-git-send-email-mdavidsaver@gmail.com> In-Reply-To: <1447031505-12477-1-git-send-email-mdavidsaver@gmail.com> References: <1447031505-12477-1-git-send-email-mdavidsaver@gmail.com> Subject: [Qemu-devel] [PATCH 12/18] armv7m: simpler/faster exception start List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Crosthwaite , qemu-arm@nongnu.org, Michael Davidsaver No need to bounce through EXCP_IRQ handling for non-IRQ exceptions. just update CPU state directly. Signed-off-by: Michael Davidsaver --- target-arm/helper.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1d7ac43..2541890 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5433,23 +5433,21 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) /* For exceptions we just mark as pending on the NVIC, and let that handle it. */ - /* TODO: Need to escalate if the current priority is higher than the - one we're raising. */ switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - return; + break; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); - return; + break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: /* TODO: if we implemented the MPU registers, this is where we * should set the MMFAR, etc from exception.fsr and exception.vaddress. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); - return; + break; case EXCP_BKPT: if (semihosting_enabled()) { int nr; @@ -5466,7 +5464,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG); return; case EXCP_IRQ: - env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic); break; case EXCP_EXCEPTION_EXIT: do_v7m_exception_exit(env); @@ -5476,6 +5473,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } + armv7m_nvic_acknowledge_irq(env->nvic); + + qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); + /* Align stack pointer. */ /* ??? Should only do this if Configuration Control Register STACKALIGN bit is set. */ -- 2.1.4