[Qemu-devel] [PATCH 03/18] armv7m: Complain about incorrect exception table entries.

[Michael Davidsaver <mdavidsaver@gmail.com>]

For -M  These should always be thumb mode.
Log a message if this is seen.

Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com>
---
 target-arm/helper.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4408100..4178400 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5396,7 +5396,8 @@ static void do_v7m_exception_exit(CPUARMState *env)
         qemu_log_mask(LOG_GUEST_ERROR,
                       "M profile return from interrupt with misaligned "
                       "PC is UNPREDICTABLE\n");
-        /* Actual hardware seems to ignore the lsbit, and there are several
+        /* The ARM calls for UsageFault when the T bit isn't set, but
+         * actual hardware seems to ignore the lsbit, and there are several
          * RTOSes out there which incorrectly assume the r15 in the stack
          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
          */
@@ -5498,6 +5499,12 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
     env->regs[15] = addr & 0xfffffffe;
     env->thumb = addr & 1;
+    if (!env->thumb) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "M profile interrupt handler %d with incorrect "
+                      "instruction mode in PC is UNPREDICTABLE\n",
+                      env->v7m.exception);
+    }
 }
 
 /* Function used to synchronize QEMU's AArch64 register set with AArch32
-- 
2.1.4