From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52290) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zvb1O-0001Kb-5t for qemu-devel@nongnu.org; Sun, 08 Nov 2015 20:13:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zvb1K-0007u2-3H for qemu-devel@nongnu.org; Sun, 08 Nov 2015 20:13:22 -0500 From: Michael Davidsaver Date: Sun, 8 Nov 2015 20:11:30 -0500 Message-Id: <1447031505-12477-4-git-send-email-mdavidsaver@gmail.com> In-Reply-To: <1447031505-12477-1-git-send-email-mdavidsaver@gmail.com> References: <1447031505-12477-1-git-send-email-mdavidsaver@gmail.com> Subject: [Qemu-devel] [PATCH 03/18] armv7m: Complain about incorrect exception table entries. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Crosthwaite , qemu-arm@nongnu.org, Michael Davidsaver For -M These should always be thumb mode. Log a message if this is seen. Signed-off-by: Michael Davidsaver --- target-arm/helper.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4408100..4178400 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5396,7 +5396,8 @@ static void do_v7m_exception_exit(CPUARMState *env) qemu_log_mask(LOG_GUEST_ERROR, "M profile return from interrupt with misaligned " "PC is UNPREDICTABLE\n"); - /* Actual hardware seems to ignore the lsbit, and there are several + /* The ARM calls for UsageFault when the T bit isn't set, but + * actual hardware seems to ignore the lsbit, and there are several * RTOSes out there which incorrectly assume the r15 in the stack * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value. */ @@ -5498,6 +5499,12 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4); env->regs[15] = addr & 0xfffffffe; env->thumb = addr & 1; + if (!env->thumb) { + qemu_log_mask(LOG_GUEST_ERROR, + "M profile interrupt handler %d with incorrect " + "instruction mode in PC is UNPREDICTABLE\n", + env->v7m.exception); + } } /* Function used to synchronize QEMU's AArch64 register set with AArch32 -- 2.1.4