From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52322) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zvb1P-0001L3-Fi for qemu-devel@nongnu.org; Sun, 08 Nov 2015 20:13:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zvb1N-0007wL-Aa for qemu-devel@nongnu.org; Sun, 08 Nov 2015 20:13:23 -0500 From: Michael Davidsaver Date: Sun, 8 Nov 2015 20:11:35 -0500 Message-Id: <1447031505-12477-9-git-send-email-mdavidsaver@gmail.com> In-Reply-To: <1447031505-12477-1-git-send-email-mdavidsaver@gmail.com> References: <1447031505-12477-1-git-send-email-mdavidsaver@gmail.com> Subject: [Qemu-devel] [PATCH 08/18] armv7m: fix RETTOBASE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Crosthwaite , qemu-arm@nongnu.org, Michael Davidsaver The polarity is reversed, and it should include internal exceptions. Should be set when # of active exceptions <= 1. Signed-off-by: Michael Davidsaver --- hw/intc/armv7m_nvic.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 30e349e..3b10dee 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -432,16 +432,20 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) val = cpu->env.v7m.exception; /* VECTPENDING */ val |= (cpu->env.v7m.pending << 12)&0x1ff; - /* ISRPENDING and RETTOBASE */ + /* ISRPENDING - Set it any externel IRQ pending (vector>=16) */ for (irq = 16; irq < s->num_irq; irq++) { if (s->vectors[irq].pending) { val |= (1 << 22); break; } + } + /* RETTOBASE - Set if no (other) handler is active */ + for (irq = 1; irq < s->num_irq; irq++) { if (irq != cpu->env.v7m.exception && s->vectors[irq].active) { - val |= (1 << 11); + val |= (1 << 11); /* some other handler is active */ } } + val ^= (1<<11); /* invert */ /* PENDSTSET */ if (s->vectors[ARMV7M_EXCP_SYSTICK].pending) { val |= (1 << 26); @@ -454,6 +458,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) if (s->vectors[ARMV7M_EXCP_NMI].pending) { val |= (1 << 31); } + /* ISRPREEMPT not implemented */ return val; case 0xd08: /* Vector Table Offset. */ return cpu->env.v7m.vecbase; @@ -588,10 +593,14 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) qemu_irq_pulse(s->sysresetreq); } if (value & 2) { - qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "Setting VECTCLRACTIVE when not in DEBUG mode " + "is UNPREDICTABLE\n"); } if (value & 1) { - qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n"); + qemu_log_mask(LOG_GUEST_ERROR, + "Setting VECTRESET when not in DEBUG mode " + "is UNPREDICTABLE\n"); } if (value & 0x700) { unsigned i; -- 2.1.4