From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40672) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zw8vy-00077C-Tx for qemu-devel@nongnu.org; Tue, 10 Nov 2015 08:26:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zw8vy-0007c8-1V for qemu-devel@nongnu.org; Tue, 10 Nov 2015 08:26:02 -0500 From: Rabin Vincent Date: Tue, 10 Nov 2015 14:25:47 +0100 Message-ID: <1447161947-22542-1-git-send-email-rabin.vincent@axis.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH] nand: fix address overflow List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: kwolf@redhat.com Cc: qemu-devel@nongnu.org, qemu-block@nongnu.org, Rabin Vincent The shifts of the address mask and value shift beyond 32 bits when there are 5 address cycles. Signed-off-by: Rabin Vincent --- hw/block/nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/block/nand.c b/hw/block/nand.c index 61d2cec..a68266f 100644 --- a/hw/block/nand.c +++ b/hw/block/nand.c @@ -522,8 +522,8 @@ void nand_setio(DeviceState *dev, uint32_t value) if (s->ale) { unsigned int shift = s->addrlen * 8; - unsigned int mask = ~(0xff << shift); - unsigned int v = value << shift; + uint64_t mask = ~(0xffull << shift); + uint64_t v = (uint64_t)value << shift; s->addr = (s->addr & mask) | v; s->addrlen ++; -- 1.7.10.4