From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zw9L2-0004Z3-D8 for qemu-devel@nongnu.org; Tue, 10 Nov 2015 08:51:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zw9Kx-0006IV-7t for qemu-devel@nongnu.org; Tue, 10 Nov 2015 08:51:56 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35389) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zw9Kw-0006HI-Ry for qemu-devel@nongnu.org; Tue, 10 Nov 2015 08:51:51 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Zw9Kt-0006w4-Hj for qemu-devel@nongnu.org; Tue, 10 Nov 2015 13:51:47 +0000 From: Peter Maydell Date: Tue, 10 Nov 2015 13:51:42 +0000 Message-Id: <1447163507-26627-3-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1447163507-26627-1-git-send-email-peter.maydell@linaro.org> References: <1447163507-26627-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 2/7] hw/intc/arm_gic: Remove the definition of NUM_CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Wei Huang arm_gic.c retrieves CPU number using either NUM_CPU(s) or s->num_cpu. Such mixed-uses make source code inconsistent. This patch removes NUM_CPU(s), which was defined for MPCore tweak long ago, and instead favors s->num_cpu. The source is more consistent after this small tweak. Reviewed-by: Andreas Färber Signed-off-by: Wei Huang Reviewed-by: Michael Tokarev Message-id: 1446744293-32365-1-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 8bad132..d71aeb8 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -35,8 +35,6 @@ static const uint8_t gic_id[] = { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -#define NUM_CPU(s) ((s)->num_cpu) - static inline int gic_get_current_cpu(GICState *s) { if (s->num_cpu > 1) { @@ -64,7 +62,7 @@ void gic_update(GICState *s) int cpu; int cm; - for (cpu = 0; cpu < NUM_CPU(s); cpu++) { + for (cpu = 0; cpu < s->num_cpu; cpu++) { cm = 1 << cpu; s->current_pending[cpu] = 1023; if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) @@ -567,7 +565,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) if (offset == 4) /* Interrupt Controller Type Register */ return ((s->num_irq / 32) - 1) - | ((NUM_CPU(s) - 1) << 5) + | ((s->num_cpu - 1) << 5) | (s->security_extn << 10); if (offset < 0x08) return 0; @@ -1284,7 +1282,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) * GIC v2 defines a larger memory region (0x1000) so this will need * to be extended when we implement A15. */ - for (i = 0; i < NUM_CPU(s); i++) { + for (i = 0; i < s->num_cpu; i++) { s->backref[i] = s; memory_region_init_io(&s->cpuiomem[i+1], OBJECT(s), &gic_cpu_ops, &s->backref[i], "gic_cpu", 0x100); -- 1.9.1