From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwJJj-0003kE-Or for qemu-devel@nongnu.org; Tue, 10 Nov 2015 19:31:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZwJJh-0004oc-Fd for qemu-devel@nongnu.org; Tue, 10 Nov 2015 19:31:15 -0500 From: Benjamin Herrenschmidt Date: Wed, 11 Nov 2015 11:28:03 +1100 Message-Id: <1447201710-10229-51-git-send-email-benh@kernel.crashing.org> In-Reply-To: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> Subject: [Qemu-devel] [PATCH 50/77] ppc: Update LPCR definitions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org Includes all the bits up to ISA 2.07 Signed-off-by: Benjamin Herrenschmidt --- target-ppc/cpu.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index a7236cf..ca6c961 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -493,12 +493,16 @@ struct ppc_slb_t { #define LPCR_VPM1 (1ull << (63-1)) #define LPCR_ISL (1ull << (63-2)) #define LPCR_KBV (1ull << (63-3)) +#define LPCR_DPFD_SHIFT (63-11) +#define LPCR_DPFD (0x3ull << LPCR_DPFD_SHIFT) +#define LPCR_VRMASD_SHIFT (63-16) +#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) +#define LPCR_RMLS_SHIFT (63-37) +#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) #define LPCR_ILE (1ull << (63-38)) -#define LPCR_MER (1ull << (63-52)) -#define LPCR_LPES0 (1ull << (63-60)) -#define LPCR_LPES1 (1ull << (63-61)) #define LPCR_AIL_SHIFT (63-40) /* Alternate interrupt location */ #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) +#define LPCR_ONL (1ull << (63-45)) #define LPCR_P7_PECE0 (1ull << (63-49)) #define LPCR_P7_PECE1 (1ull << (63-50)) #define LPCR_P7_PECE2 (1ull << (63-51)) @@ -507,6 +511,12 @@ struct ppc_slb_t { #define LPCR_P8_PECE2 (1ull << (63-49)) #define LPCR_P8_PECE3 (1ull << (63-50)) #define LPCR_P8_PECE4 (1ull << (63-51)) +#define LPCR_MER (1ull << (63-52)) +#define LPCR_TC (1ull << (63-54)) +#define LPCR_LPES0 (1ull << (63-60)) +#define LPCR_LPES1 (1ull << (63-61)) +#define LPCR_RMI (1ull << (63-62)) +#define LPCR_HDICE (1ull << (63-63)) #define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1) -- 2.5.0