From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39070) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZwJKP-00057C-FS for qemu-devel@nongnu.org; Tue, 10 Nov 2015 19:32:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZwJKO-00059K-Lc for qemu-devel@nongnu.org; Tue, 10 Nov 2015 19:31:57 -0500 From: Benjamin Herrenschmidt Date: Wed, 11 Nov 2015 11:28:23 +1100 Message-Id: <1447201710-10229-71-git-send-email-benh@kernel.crashing.org> In-Reply-To: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> Subject: [Qemu-devel] [PATCH 70/77] ppc: Add dummy CIABR SPR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org We should implement HW breakpoint/watchpoint, qemu supports them... Signed-off-by: Benjamin Herrenschmidt --- target-ppc/cpu.h | 1 + target-ppc/translate_init.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 334fcfe..bf8892a 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1402,6 +1402,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) #define SPR_DAWR (0x0B4) #define SPR_MPPR (0x0B8) #define SPR_RPR (0x0BA) +#define SPR_CIABR (0x0BB) #define SPR_DAWRX (0x0BC) #define SPR_HFSCR (0x0BE) #define SPR_VRSAVE (0x100) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b1eba73..b5fd076 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7629,6 +7629,11 @@ static void gen_spr_book3s_207_dbg(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_generic, 0x00000000); + spr_register_kvm_hv(env, SPR_CIABR, "CIABR", + SPR_NOACCESS, SPR_NOACCESS, + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic, + KVM_REG_PPC_CIABR, 0x00000000); } static void gen_spr_970_dbg(CPUPPCState *env) -- 2.5.0