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From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Mon, 16 Nov 2015 21:16:08 +1100
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 03/77] ppc: Do some batching of
 TCG tlb flushes
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To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

On Mon, 2015-11-16 at 16:00 +1100, David Gibson wrote:
>=C2=A0
> > =C2=A0//#define DEBUG_MMU
> > =C2=A0//#define DEBUG_BATS
> > @@ -1940,6 +1941,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case POWERPC_MMU_2_03:
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case POWERPC_MMU_2_06:
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case POWERPC_MMU_2_07:
> > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0env->tlb_need_flush =
=3D 0;
> > =C2=A0#endif /* defined(TARGET_PPC64) */
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0tlb_flush(CPU(c=
pu), 1);
> > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0break;
>=20
> Any particular reason you're leaving this one as an immediate rather
> than deferred flush?

A couple yes. It's mostly unused on server CPUs (we don't do tlbia),
and it's used by ppc_cpu_reset(). In that latter case, I like having
everything really cleaned up ...=C2=A0

> Should you be clearing the pending flush flag cpu_reset()?

That should happen as a result of the above.

Cheers,
Ben.