From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37654) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZyKfM-0004yZ-Dy for qemu-devel@nongnu.org; Mon, 16 Nov 2015 09:21:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZyKfL-00083Q-LE for qemu-devel@nongnu.org; Mon, 16 Nov 2015 09:21:56 -0500 From: Peter Maydell Date: Mon, 16 Nov 2015 14:05:23 +0000 Message-Id: <1447682723-3977-20-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> References: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 19/19] HACK: rearrange the virt memory map to suit OP-TEE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-arm@nongnu.org, Paolo Bonzini , "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= The current OP-TEE codebase expects the secure UART to be at 0x09010000 and irq 2 (it is based on an old non-upstream patch to add a second uart, and upstream used that memory map area for something else). When the TZ support is upstream in QEMU we can move OP-TEE on to a proper upstream QEMU and update it to use the new UART location, but for now this hack patch allows running a more-or-less unmodified OP-TEE. Put the secure UART at the address and irq where OP-TEE expects it, moving some other devices down to make space. Signed-off-by: Peter Maydell --- hw/arm/virt.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 623e835..ced42be 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -118,9 +118,9 @@ static const MemMapEntry a15memmap[] = { /* This redistributor space allows up to 2*64kB*123 CPUs */ [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, [VIRT_UART] = { 0x09000000, 0x00001000 }, - [VIRT_RTC] = { 0x09010000, 0x00001000 }, - [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, - [VIRT_SECURE_UART] = { 0x09030000, 0x00001000 }, + [VIRT_RTC] = { 0x09020000, 0x00001000 }, + [VIRT_FW_CFG] = { 0x09030000, 0x00000018 }, + [VIRT_SECURE_UART] = { 0x09010000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -134,9 +134,9 @@ static const MemMapEntry a15memmap[] = { static const int a15irqmap[] = { [VIRT_UART] = 1, - [VIRT_RTC] = 2, - [VIRT_PCIE] = 3, /* ... to 6 */ - [VIRT_SECURE_UART] = 7, + [VIRT_RTC] = 3, + [VIRT_PCIE] = 4, /* ... to 7 */ + [VIRT_SECURE_UART] = 2, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ -- 1.9.1