From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45499) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zylf3-0006ds-Hh for qemu-devel@nongnu.org; Tue, 17 Nov 2015 14:11:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zylf0-0004iS-EM for qemu-devel@nongnu.org; Tue, 17 Nov 2015 14:11:25 -0500 Received: from mx1.redhat.com ([209.132.183.28]:57486) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zylf0-0004iO-8o for qemu-devel@nongnu.org; Tue, 17 Nov 2015 14:11:22 -0500 From: Eduardo Habkost Date: Tue, 17 Nov 2015 17:11:08 -0200 Message-Id: <1447787469-29776-2-git-send-email-ehabkost@redhat.com> In-Reply-To: <1447787469-29776-1-git-send-email-ehabkost@redhat.com> References: <1447787469-29776-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [PULL 1/2] target-i386: Fix mulx for identical target regs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Paolo Bonzini , Richard Henderson , qemu-devel@nongnu.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Richard Henderson The Intel specification clearly indicates that the low part of the result is written first and the high part of the result is written second; thus if ModRM:reg and VEX.vvvv are identical, the final result should be the high part of the result. At present, TCG may either produce incorrect results or crash with --enable-checking. Reported-by: Toni Nedialkov Reported-by: Max Reitz Signed-off-by: Richard Henderson Signed-off-by: Eduardo Habkost --- target-i386/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index fbe4f80..a3dd167 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -3848,8 +3848,10 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, break; #ifdef TARGET_X86_64 case MO_64: - tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg], + tcg_gen_mulu2_i64(cpu_T[0], cpu_T[1], cpu_T[0], cpu_regs[R_EDX]); + tcg_gen_mov_i64(cpu_regs[s->vex_v], cpu_T[0]); + tcg_gen_mov_i64(cpu_regs[reg], cpu_T[1]); break; #endif } -- 2.1.0