[Qemu-devel] [PATCH] target-arm: Priority masking with basepri on v7m

[Qemu-devel] [PATCH] target-arm: Priority masking with basepri on v7m

[François Baldassari]

On armv7m mcus, the BASEPRI register can be set to mask interrupts
above a certain priority.

This changeset implements that functionality by way of the NVIC which
ultimately sets the interrupt mask in the GIC.

Signed-off-by: François Baldassari <francois@pebble.com>
---
 hw/intc/arm_gic.c      |  2 +-
 hw/intc/armv7m_nvic.c  | 11 +++++++++++
 hw/intc/gic_internal.h |  4 ++++
 target-arm/cpu.h       |  1 +
 target-arm/helper.c    |  2 ++
 5 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d71aeb8..27b4906 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -399,7 +399,7 @@ static uint32_t gic_get_priority(GICState *s, int cpu, int irq,
     return prio;
 }
 
-static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
+void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
                                   MemTxAttrs attrs)
 {
     if (s->security_extn && !attrs.secure) {
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 6fc167e..d1aa556 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -148,6 +148,17 @@ void armv7m_nvic_complete_irq(void *opaque, int irq)
     gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED);
 }
 
+
+void armv7m_nvic_set_priority_mask(void *opaque, uint16_t mask)
+{
+    nvic_state *s = (nvic_state *)opaque;
+    if (mask == 0) {
+        /* 0 is used to disable the priority mask */
+        mask = 0x100;
+    }
+    gic_set_priority_mask(&s->gic, 0, mask, MEMTXATTRS_UNSPECIFIED);
+}
+
 static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
 {
     ARMCPU *cpu;
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 20c1e8a..995f337 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -84,6 +84,10 @@ void gic_update(GICState *s);
 void gic_init_irqs_and_distributor(GICState *s);
 void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
                       MemTxAttrs attrs);
+void gic_set_priority_mask(GICState *s,
+                           int cpu,
+                           uint8_t pmask,
+                           MemTxAttrs attrs);
 
 static inline bool gic_test_pending(GICState *s, int irq, int cm)
 {
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 815fef8..fb7dc61 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1034,6 +1034,7 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
 void armv7m_nvic_set_pending(void *opaque, int irq);
 int armv7m_nvic_acknowledge_irq(void *opaque);
 void armv7m_nvic_complete_irq(void *opaque, int irq);
+void armv7m_nvic_set_priority_mask(void *opaque, uint16_t mask);
 
 /* Interface for defining coprocessor registers.
  * Registers are defined in tables of arm_cp_reginfo structs
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4ecae61..27807e9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -7449,11 +7449,13 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
         break;
     case 17: /* BASEPRI */
         env->v7m.basepri = val & 0xff;
+        armv7m_nvic_set_priority_mask(env->nvic, env->v7m.basepri);
         break;
     case 18: /* BASEPRI_MAX */
         val &= 0xff;
         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
             env->v7m.basepri = val;
+            armv7m_nvic_set_priority_mask(env->nvic, env->v7m.basepri);
         break;
     case 19: /* FAULTMASK */
         if (val & 1) {
-- 
2.4.0

Re: [Qemu-devel] [PATCH] target-arm: Priority masking with basepri on v7m

[Peter Maydell]

On 17 November 2015 at 21:40, François Baldassari
<francois@getpebble.com> wrote:
> On armv7m mcus, the BASEPRI register can be set to mask interrupts
> above a certain priority.
>
> This changeset implements that functionality by way of the NVIC which
> ultimately sets the interrupt mask in the GIC.
>
> Signed-off-by: François Baldassari <francois@pebble.com>

There are a lot of problems with our NVIC priority handling
right now. You might like to take a look at the patch set that
Michael Davidsaver sent out earlier this month:
https://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg01542.html

That has some problems but I think it's probably the way we're
going to go to fix up the NVIC.

thanks
-- PMM

Re: [Qemu-devel] [PATCH] target-arm: Priority masking with basepri on v7m

[Francois Baldassari]

[-- Attachment #1: Type: text/plain, Size: 1043 bytes --]

Thanks for the swift reply.

Michael's changes look very good indeed. Thank you for pointing them out.

No need to consider this any further then.

Cheers,

François.

On Tue, Nov 17, 2015 at 1:49 PM, Peter Maydell <peter.maydell@linaro.org>
wrote:

> On 17 November 2015 at 21:40, François Baldassari
> <francois@getpebble.com> wrote:
> > On armv7m mcus, the BASEPRI register can be set to mask interrupts
> > above a certain priority.
> >
> > This changeset implements that functionality by way of the NVIC which
> > ultimately sets the interrupt mask in the GIC.
> >
> > Signed-off-by: François Baldassari <francois@pebble.com>
>
> There are a lot of problems with our NVIC priority handling
> right now. You might like to take a look at the patch set that
> Michael Davidsaver sent out earlier this month:
> https://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg01542.html
>
> That has some problems but I think it's probably the way we're
> going to go to fix up the NVIC.
>
> thanks
> -- PMM
>

[-- Attachment #2: Type: text/html, Size: 1722 bytes --]

Re: [Qemu-devel] [Qemu-arm] [PATCH] target-arm: Priority masking with basepri on v7m

[Peter Crosthwaite]

On Tue, Nov 17, 2015 at 1:52 PM, Francois Baldassari
<francois@pebble.com> wrote:
> Thanks for the swift reply.
>
> Michael's changes look very good indeed. Thank you for pointing them out.
>

If you have tested them as working and fixing a problem for you, you
should contribute a tested-by tag to the series.

Regards,
Peter

> No need to consider this any further then.
>
> Cheers,
>
> François.
>
> On Tue, Nov 17, 2015 at 1:49 PM, Peter Maydell <peter.maydell@linaro.org>
> wrote:
>>
>> On 17 November 2015 at 21:40, François Baldassari
>> <francois@getpebble.com> wrote:
>> > On armv7m mcus, the BASEPRI register can be set to mask interrupts
>> > above a certain priority.
>> >
>> > This changeset implements that functionality by way of the NVIC which
>> > ultimately sets the interrupt mask in the GIC.
>> >
>> > Signed-off-by: François Baldassari <francois@pebble.com>
>>
>> There are a lot of problems with our NVIC priority handling
>> right now. You might like to take a look at the patch set that
>> Michael Davidsaver sent out earlier this month:
>> https://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg01542.html
>>
>> That has some problems but I think it's probably the way we're
>> going to go to fix up the NVIC.
>>
>> thanks
>> -- PMM
>
>

Re: [Qemu-devel] [Qemu-arm] [PATCH] target-arm: Priority masking with basepri on v7m

[Francois Baldassari]

Hi Peter,

I must be missing something obvious, but I do not have the original
email thread (I was not subscribed at the time) and thus am finding it
exceedingly difficult to apply the patches using git-am.

I would happily test the patches otherwise.

Any guidance here?

François

On Wed, Nov 18, 2015 at 9:56 AM, Peter Crosthwaite
<crosthwaitepeter@gmail.com> wrote:
> On Tue, Nov 17, 2015 at 1:52 PM, Francois Baldassari
> <francois@pebble.com> wrote:
>> Thanks for the swift reply.
>>
>> Michael's changes look very good indeed. Thank you for pointing them out.
>>
>
> If you have tested them as working and fixing a problem for you, you
> should contribute a tested-by tag to the series.
>
> Regards,
> Peter
>
>> No need to consider this any further then.
>>
>> Cheers,
>>
>> François.
>>
>> On Tue, Nov 17, 2015 at 1:49 PM, Peter Maydell <peter.maydell@linaro.org>
>> wrote:
>>>
>>> On 17 November 2015 at 21:40, François Baldassari
>>> <francois@getpebble.com> wrote:
>>> > On armv7m mcus, the BASEPRI register can be set to mask interrupts
>>> > above a certain priority.
>>> >
>>> > This changeset implements that functionality by way of the NVIC which
>>> > ultimately sets the interrupt mask in the GIC.
>>> >
>>> > Signed-off-by: François Baldassari <francois@pebble.com>
>>>
>>> There are a lot of problems with our NVIC priority handling
>>> right now. You might like to take a look at the patch set that
>>> Michael Davidsaver sent out earlier this month:
>>> https://lists.nongnu.org/archive/html/qemu-devel/2015-11/msg01542.html
>>>
>>> That has some problems but I think it's probably the way we're
>>> going to go to fix up the NVIC.
>>>
>>> thanks
>>> -- PMM
>>
>>

Re: [Qemu-devel] [Qemu-arm] [PATCH] target-arm: Priority masking with basepri on v7m

[Peter Maydell]

On 18 November 2015 at 20:30, Francois Baldassari <francois@pebble.com> wrote:
[regarding Michael's M profile NVIC patchset]
> I must be missing something obvious, but I do not have the original
> email thread (I was not subscribed at the time) and thus am finding it
> exceedingly difficult to apply the patches using git-am.
>
> I would happily test the patches otherwise.

For a big patchset like this the easiest thing is to just ask
Michael if he has a public git repo with the patches in (I've
cc'd him).

Otherwise there are a couple of tools: you can use patchwork:
http://patchwork.ozlabs.org/project/qemu-devel/list/
(you need to search for the relevant patches and download the
'mbox' files for them to 'git am' one at a time; unfortunately
patchwork doesn't yet know about patch series to let you download
a series all at once). Or you can use the 'patches' tool:
https://github.com/aliguori/patches
That needs to be installed locally, but it does know about
patch series and it can directly apply a whole series to your
local git tree.

For a one-off use the patchwork website is easier, since
there's no need to install anything locally. (It's also
more forgiving of misformatted patch emails.) If you're going
to make a habit of applying patches from the mailing list,
the patches tool is easier to use and will repay the up-front
effort of downloading it and figuring out its UI.

thanks
-- PMM

Re: [Qemu-devel] [Qemu-arm] [PATCH] target-arm: Priority masking with basepri on v7m

[Michael Davidsaver]

On 11/18/2015 02:41 PM, Peter Maydell wrote:
> For a big patchset like this the easiest thing is to just ask
> Michael if he has a public git repo with the patches in (I've
> cc'd him).

https://github.com/mdavidsaver/qemu/tree/fixirq

The posted patches were

https://github.com/qemu/qemu/compare/c4a7bf54e588ff2de9fba0898b686156251b2063...dd7fc89e3c70b1e0074efa41e3ca89f5cee43054

This branch also has more recent changesets which weren't posted.  Some
of this will be posted in future (MPU stuff), and some should just be
ignored (qtest fumbling).