[Qemu-devel] [PULL 0/3] target-arm queue

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Just three fairly small bugfixes...

-- PMM


The following changes since commit 8f280309030331a912fd8924c129d8bd59e1bdc7:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2015-11-18 17:07:24 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151119

for you to fetch changes up to ce8a1b5449cd8c4c2831abb581d3208c3a3745a0:

  target-arm: Update condexec before arch BP check in AA32 translation (2015-11-19 12:51:08 +0000)

----------------------------------------------------------------
target-arm queue:
 * add missing condexec updates when emulating architectural breakpoints
   and coprocessor access checks in Thumb translation (could in theory
   cause problems when these happened inside a Thumb IT block and an
   exception was taken)
 * arm_gic: correctly restore nested IRQ priority

----------------------------------------------------------------
François Baldassari (1):
      hw/arm_gic: Correctly restore nested irq priority

Sergey Fedorov (2):
      target-arm: Update condexec before CP access check in AA32 translation
      target-arm: Update condexec before arch BP check in AA32 translation

 hw/intc/arm_gic.c      | 4 ++--
 target-arm/translate.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

[Qemu-devel] [PULL 1/3] hw/arm_gic: Correctly restore nested irq priority

[Peter Maydell]

From: François Baldassari <francois@pebble.com>

Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.

Signed-off-by: François Baldassari <francois@pebble.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d71aeb8..13e297d 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
     int bitno = preemption_level % 32;
 
     if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
-        s->nsapr[regno][cpu] &= (1 << bitno);
+        s->nsapr[regno][cpu] |= (1 << bitno);
     } else {
-        s->apr[regno][cpu] &= (1 << bitno);
+        s->apr[regno][cpu] |= (1 << bitno);
     }
 
     s->running_priority[cpu] = prio;
-- 
1.9.1

[Qemu-devel] [PULL 2/3] target-arm: Update condexec before CP access check in AA32 translation

[Peter Maydell]

From: Sergey Fedorov <serge.fdrv@gmail.com>

Coprocessor access instructions are allowed inside IT block.
gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
bits should be updated before.

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1447767527-21268-2-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4351854..739f373 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
                 break;
             }
 
+            gen_set_condexec(s);
             gen_set_pc_im(s, s->pc - 4);
             tmpptr = tcg_const_ptr(ri);
             tcg_syn = tcg_const_i32(syndrome);
-- 
1.9.1

[Qemu-devel] [PULL 3/3] target-arm: Update condexec before arch BP check in AA32 translation

[Peter Maydell]

From: Sergey Fedorov <serge.fdrv@gmail.com>

Architectural breakpoint check could raise an exceptions, thus condexec
bits should be updated before calling gen_helper_check_breakpoints().

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1447767527-21268-3-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 739f373..5d22879 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11374,6 +11374,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
                 if (bp->pc == dc->pc) {
                     if (bp->flags & BP_CPU) {
+                        gen_set_condexec(dc);
                         gen_set_pc_im(dc, dc->pc);
                         gen_helper_check_breakpoints(cpu_env);
                         /* End the TB early; it's likely not going to be executed */
-- 
1.9.1

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

On 19 November 2015 at 13:31, Peter Maydell <peter.maydell@linaro.org> wrote:
> Just three fairly small bugfixes...
>
> -- PMM
>
>
> The following changes since commit 8f280309030331a912fd8924c129d8bd59e1bdc7:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2015-11-18 17:07:24 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151119
>
> for you to fetch changes up to ce8a1b5449cd8c4c2831abb581d3208c3a3745a0:
>
>   target-arm: Update condexec before arch BP check in AA32 translation (2015-11-19 12:51:08 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * add missing condexec updates when emulating architectural breakpoints
>    and coprocessor access checks in Thumb translation (could in theory
>    cause problems when these happened inside a Thumb IT block and an
>    exception was taken)
>  * arm_gic: correctly restore nested IRQ priority
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Last arm patches for rc3...

thanks
-- PMM

The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95:

  Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126

for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d:

  net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000)

----------------------------------------------------------------
target-arm queue:
 * some updates to MAINTAINERS file entries
 * cadence_gem: Remove an incorrect assert()

----------------------------------------------------------------
Edgar E. Iglesias (1):
      net: cadence_gem: Remove incorrect assert()

Eric Auger (1):
      MAINTAINERS: Add an ARM SMMU section

Thomas Huth (1):
      MAINTAINERS: Assign some more files in the hw/arm/ directory

 hw/net/cadence_gem.c |  1 -
 MAINTAINERS          | 23 +++++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

On Mon, 26 Nov 2018 at 14:00, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Last arm patches for rc3...
>
> thanks
> -- PMM
>
> The following changes since commit 72138f9bf5d8c316043b0d2cc7a674f70930cf95:
>
>   Merge remote-tracking branch 'remotes/gkurz/tags/for-upstream' into staging (2018-11-26 11:46:04 +0000)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181126
>
> for you to fetch changes up to 58102ce7fbb2362aa53984aabcf684d164da2d9d:
>
>   net: cadence_gem: Remove incorrect assert() (2018-11-26 13:41:42 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * some updates to MAINTAINERS file entries
>  * cadence_gem: Remove an incorrect assert()
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for my target-arm queue; please pull.

The following changes since commit f638f0d3ae214d995cdd94578195700cda24597b:

  qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs (2012-03-29 11:10:08 +0400)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Andreas Färber (2):
      target-arm: Drop cpu_arm_close()
      target-arm: Minimalistic CPU QOM'ification

Andrew Towers (1):
      ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.

 Makefile.target        |    1 +
 target-arm/cpu-qom.h   |   71 ++++++++++++++++++++++++++++++++++++++++++++++++
 target-arm/cpu.c       |   60 ++++++++++++++++++++++++++++++++++++++++
 target-arm/cpu.h       |    3 +-
 target-arm/helper.c    |   14 +++++----
 target-arm/translate.c |    2 +-
 6 files changed, 143 insertions(+), 8 deletions(-)
 create mode 100644 target-arm/cpu-qom.h
 create mode 100644 target-arm/cpu.c

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Blue Swirl]

On Fri, Mar 30, 2012 at 10:26, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for my target-arm queue; please pull.

Thanks, pulled.

> The following changes since commit f638f0d3ae214d995cdd94578195700cda24597b:
>
>  qemu tcg: Remove one entry of INDEX_op_ld_i64 from ppc_op_defs (2012-03-29 11:10:08 +0400)
>
> are available in the git repository at:
>  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> Andreas Färber (2):
>      target-arm: Drop cpu_arm_close()
>      target-arm: Minimalistic CPU QOM'ification
>
> Andrew Towers (1):
>      ARM: Permit any ARMv6K CPU to read the MVFR0 and MVFR1 VFP registers.
>
>  Makefile.target        |    1 +
>  target-arm/cpu-qom.h   |   71 ++++++++++++++++++++++++++++++++++++++++++++++++
>  target-arm/cpu.c       |   60 ++++++++++++++++++++++++++++++++++++++++
>  target-arm/cpu.h       |    3 +-
>  target-arm/helper.c    |   14 +++++----
>  target-arm/translate.c |    2 +-
>  6 files changed, 143 insertions(+), 8 deletions(-)
>  create mode 100644 target-arm/cpu-qom.h
>  create mode 100644 target-arm/cpu.c

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for my target-arm queue. Just three fairly
minor bug fixes this time. Please pull.

Thanks
-- PMM

The following changes since commit ae7d54d489540b49b7c13a7df7ddc220588a2ced:

  target-lm32/microblaze: Drop second CPU{LM32, MB}State typedef (2012-03-14 19:48:37 -0500)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Peter Maydell (3):
      target-arm: Fix typo in ARM946 cp15 c5 handling
      target-arm: Clear IT bits when taking exceptions in v7M
      target-arm: Decode SETEND correctly in Thumb

 target-arm/helper.c    |    5 ++-
 target-arm/translate.c |   63 ++++++++++++++++++++++++++++++-----------------
 2 files changed, 43 insertions(+), 25 deletions(-)

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Blue Swirl]

On Fri, Mar 16, 2012 at 18:21, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for my target-arm queue. Just three fairly
> minor bug fixes this time. Please pull.

Thanks, pulled.

> Thanks
> -- PMM
>
> The following changes since commit ae7d54d489540b49b7c13a7df7ddc220588a2ced:
>
>  target-lm32/microblaze: Drop second CPU{LM32, MB}State typedef (2012-03-14 19:48:37 -0500)
>
> are available in the git repository at:
>  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> Peter Maydell (3):
>      target-arm: Fix typo in ARM946 cp15 c5 handling
>      target-arm: Clear IT bits when taking exceptions in v7M
>      target-arm: Decode SETEND correctly in Thumb
>
>  target-arm/helper.c    |    5 ++-
>  target-arm/translate.c |   63 ++++++++++++++++++++++++++++++-----------------
>  2 files changed, 43 insertions(+), 25 deletions(-)

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Pending target-arm patches; not very many, but seems better to
commit them now, since there might be further trustzone related
patches that would have to sit on top of these. Please pull.

The following changes since commit c47f3223658119219bbe0b8d09da733d1c06e76f:

  Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into staging (2012-01-04 10:06:25 -0600)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Mark Langsdorf (1):
      arm: add dummy A9-specific cp15 registers

Peter Maydell (2):
      target-arm: Don't use cpu_single_env in bank_number()
      target-arm: Ignore attempts to set invalid modes in CPSR

 target-arm/cpu.h     |    6 +++-
 target-arm/helper.c  |   90 ++++++++++++++++++++++++++++++++++++++++++++++----
 target-arm/machine.c |    6 +++
 3 files changed, 94 insertions(+), 8 deletions(-)

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Aurelien Jarno]

On Thu, Jan 05, 2012 at 04:44:31PM +0000, Peter Maydell wrote:
> Pending target-arm patches; not very many, but seems better to
> commit them now, since there might be further trustzone related
> patches that would have to sit on top of these. Please pull.
> 
> The following changes since commit c47f3223658119219bbe0b8d09da733d1c06e76f:
> 
>   Merge remote-tracking branch 'pmaydell/arm-devs.for-upstream' into staging (2012-01-04 10:06:25 -0600)
> 
> are available in the git repository at:
> 
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
> 
> Mark Langsdorf (1):
>       arm: add dummy A9-specific cp15 registers
> 
> Peter Maydell (2):
>       target-arm: Don't use cpu_single_env in bank_number()
>       target-arm: Ignore attempts to set invalid modes in CPSR
> 
>  target-arm/cpu.h     |    6 +++-
>  target-arm/helper.c  |   90 ++++++++++++++++++++++++++++++++++++++++++++++----
>  target-arm/machine.c |    6 +++
>  3 files changed, 94 insertions(+), 8 deletions(-)
> 
> 

Thanks, pulled.

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net