From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33519) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZzPJL-0007SP-QJ for qemu-devel@nongnu.org; Thu, 19 Nov 2015 08:31:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZzPJK-00047r-Oy for qemu-devel@nongnu.org; Thu, 19 Nov 2015 08:31:39 -0500 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35519) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZzPJK-00046y-Ih for qemu-devel@nongnu.org; Thu, 19 Nov 2015 08:31:38 -0500 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZzPJC-0002F0-8F for qemu-devel@nongnu.org; Thu, 19 Nov 2015 13:31:30 +0000 From: Peter Maydell Date: Thu, 19 Nov 2015 13:31:28 +0000 Message-Id: <1447939890-8585-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1447939890-8585-1-git-send-email-peter.maydell@linaro.org> References: <1447939890-8585-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 1/3] hw/arm_gic: Correctly restore nested irq priority List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: François Baldassari Upon activating an interrupt, set the corresponding priority bit in the APR/NSAPR registers without touching the currently set bits. In the event of nested interrupts, the GIC will then have the information it needs to restore the priority of the pre-empted interrupt once the higher priority interrupt finishes execution. Signed-off-by: François Baldassari Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d71aeb8..13e297d 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq) int bitno = preemption_level % 32; if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { - s->nsapr[regno][cpu] &= (1 << bitno); + s->nsapr[regno][cpu] |= (1 << bitno); } else { - s->apr[regno][cpu] &= (1 << bitno); + s->apr[regno][cpu] |= (1 << bitno); } s->running_priority[cpu] = prio; -- 1.9.1