[Qemu-devel] [PULL 0/3] target-arm queue

[Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

Just three fairly small bugfixes...

-- PMM


The following changes since commit 8f280309030331a912fd8924c129d8bd59e1bdc7:

  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2015-11-18 17:07:24 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151119

for you to fetch changes up to ce8a1b5449cd8c4c2831abb581d3208c3a3745a0:

  target-arm: Update condexec before arch BP check in AA32 translation (2015-11-19 12:51:08 +0000)

----------------------------------------------------------------
target-arm queue:
 * add missing condexec updates when emulating architectural breakpoints
   and coprocessor access checks in Thumb translation (could in theory
   cause problems when these happened inside a Thumb IT block and an
   exception was taken)
 * arm_gic: correctly restore nested IRQ priority

----------------------------------------------------------------
François Baldassari (1):
      hw/arm_gic: Correctly restore nested irq priority

Sergey Fedorov (2):
      target-arm: Update condexec before CP access check in AA32 translation
      target-arm: Update condexec before arch BP check in AA32 translation

 hw/intc/arm_gic.c      | 4 ++--
 target-arm/translate.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

[Qemu-devel] [PULL 1/3] hw/arm_gic: Correctly restore nested irq priority

[Peter Maydell]

From: François Baldassari <francois@pebble.com>

Upon activating an interrupt, set the corresponding priority bit in the
APR/NSAPR registers without touching the currently set bits. In the event
of nested interrupts, the GIC will then have the information it needs to
restore the priority of the pre-empted interrupt once the higher priority
interrupt finishes execution.

Signed-off-by: François Baldassari <francois@pebble.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/intc/arm_gic.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d71aeb8..13e297d 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
     int bitno = preemption_level % 32;
 
     if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
-        s->nsapr[regno][cpu] &= (1 << bitno);
+        s->nsapr[regno][cpu] |= (1 << bitno);
     } else {
-        s->apr[regno][cpu] &= (1 << bitno);
+        s->apr[regno][cpu] |= (1 << bitno);
     }
 
     s->running_priority[cpu] = prio;
-- 
1.9.1

[Qemu-devel] [PULL 2/3] target-arm: Update condexec before CP access check in AA32 translation

[Peter Maydell]

From: Sergey Fedorov <serge.fdrv@gmail.com>

Coprocessor access instructions are allowed inside IT block.
gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
bits should be updated before.

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1447767527-21268-2-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4351854..739f373 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
                 break;
             }
 
+            gen_set_condexec(s);
             gen_set_pc_im(s, s->pc - 4);
             tmpptr = tcg_const_ptr(ri);
             tcg_syn = tcg_const_i32(syndrome);
-- 
1.9.1

[Qemu-devel] [PULL 3/3] target-arm: Update condexec before arch BP check in AA32 translation

[Peter Maydell]

From: Sergey Fedorov <serge.fdrv@gmail.com>

Architectural breakpoint check could raise an exceptions, thus condexec
bits should be updated before calling gen_helper_check_breakpoints().

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1447767527-21268-3-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 739f373..5d22879 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11374,6 +11374,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
             QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
                 if (bp->pc == dc->pc) {
                     if (bp->flags & BP_CPU) {
+                        gen_set_condexec(dc);
                         gen_set_pc_im(dc, dc->pc);
                         gen_helper_check_breakpoints(cpu_env);
                         /* End the TB early; it's likely not going to be executed */
-- 
1.9.1

Re: [Qemu-devel] [PULL 0/3] target-arm queue

[Peter Maydell]

On 19 November 2015 at 13:31, Peter Maydell <peter.maydell@linaro.org> wrote:
> Just three fairly small bugfixes...
>
> -- PMM
>
>
> The following changes since commit 8f280309030331a912fd8924c129d8bd59e1bdc7:
>
>   Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2015-11-18 17:07:24 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151119
>
> for you to fetch changes up to ce8a1b5449cd8c4c2831abb581d3208c3a3745a0:
>
>   target-arm: Update condexec before arch BP check in AA32 translation (2015-11-19 12:51:08 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * add missing condexec updates when emulating architectural breakpoints
>    and coprocessor access checks in Thumb translation (could in theory
>    cause problems when these happened inside a Thumb IT block and an
>    exception was taken)
>  * arm_gic: correctly restore nested IRQ priority
>

Applied, thanks.

-- PMM