From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 2/3] target-arm: Update condexec before CP access check in AA32 translation
Date: Thu, 19 Nov 2015 13:31:29 +0000 [thread overview]
Message-ID: <1447939890-8585-3-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1447939890-8585-1-git-send-email-peter.maydell@linaro.org>
From: Sergey Fedorov <serge.fdrv@gmail.com>
Coprocessor access instructions are allowed inside IT block.
gen_helper_access_check_cp_reg() can raise an exceptions thus condexec
bits should be updated before.
Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1447767527-21268-2-git-send-email-serge.fdrv@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4351854..739f373 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
break;
}
+ gen_set_condexec(s);
gen_set_pc_im(s, s->pc - 4);
tmpptr = tcg_const_ptr(ri);
tcg_syn = tcg_const_i32(syndrome);
--
1.9.1
next prev parent reply other threads:[~2015-11-19 13:31 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-19 13:31 [Qemu-devel] [PULL 0/3] target-arm queue Peter Maydell
2015-11-19 13:31 ` [Qemu-devel] [PULL 1/3] hw/arm_gic: Correctly restore nested irq priority Peter Maydell
2015-11-19 13:31 ` Peter Maydell [this message]
2015-11-19 13:31 ` [Qemu-devel] [PULL 3/3] target-arm: Update condexec before arch BP check in AA32 translation Peter Maydell
2015-11-19 16:25 ` [Qemu-devel] [PULL 0/3] target-arm queue Peter Maydell
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