Re: [Qemu-devel] [PATCH] vfio: Align iova also to IOMMU page size

[Alex Williamson <alex.williamson@redhat.com>]

On Thu, 2015-11-19 at 13:29 +0300, Pavel Fedin wrote:
>  Hello!
> 
> > > On some architectures TARGET_PAGE_ALIGN() is not enough to get the right
> > > alignment. For example on ARM TARGET_PAGE_BITS is 10 because some old CPUs
> > > support 1K page size, while minimum SMMU page size is 4K.
> > >
> > > This fixes problems like:
> > >
> > > 2015-11-17T07:37:42.892265Z qemu-system-aarch64: VFIO_MAP_DMA: -22
> > > 2015-11-17T07:37:42.892309Z qemu-system-aarch64: vfio_dma_map(0x223da230, 0x80002f0400,
> > 0x10fc00, 0x7f89b40400) = -22 (Invalid
> > > argument)
> > > qemu: hardware error: vfio: DMA mapping failed, unable to continue
> 
> [skip]
> 
> > I don't understand how this is supposed to work, if we align to a larger
> > size than the processor, then there are processor size pages of RAM than
> > could be handed out as DMA targets for devices, but we can't map them
> > through the IOMMU.  Thus if the guest tries to use them, we get IOMMU
> > faults in the host and likely memory corruption in the guest because the
> > device can't read or write to the page it's supposed to.  This doesn't
> > seem like the right solution.
> 
>  Well, this was my first try on the problem. I've got your idea. But i guess we should discuss the proper solution then.
>  So, i've got this problem on ARM64. On ARM64 we actually can never have 1K pages. This page size was supported only by old 32-bit ARM CPUs, up to ARMv5 IIRC, then it was dropped. Linux OS never even used it.
>  But, since qemu can emulate those ancient CPUs, TARGET_PAGE_BITS is defined to 10 for ARM. And, ARM64 and ARM32 is actually the same target for qemu, so this is why we still get it.
>  Perhaps, TARGET_PAGE_BITS should be a variable for ARM, and we should set it according to the actual used CPU. Then this IOMMU alignment problem would disappear automatically. What do you think?
>  Cc'ed Peter since he is the main ARM guy here.

Do we only see these alignments when we're emulating those old 1k page
processors?  If not, should we really be telling a 4k page VM about 1k
aligned memory?  If that's all legit, maybe we should be aligning down
rather than up, we know the host memory is at least 4k pages, so
anything in the gap between those alignments should be backed by memory,
right?  The device could theoretically get to up to 3k of memory on the
edges of each mapping, but it shouldn't touch it, the memory should be
allocated and part of the VM, could there be anything bad there?
Thanks,

Alex