[Qemu-devel] [PULL 0/4] target-arm queue

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A handful of minor ARM bugfixes...

thanks
-- PMM

The following changes since commit 229c0372cf3ca201c41d2bb121627e6752e776ad:

  Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-11-24 10:27:19 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151124

for you to fetch changes up to e14f0eb12f920fd96b9f79d15cedd437648e8667:

  target-arm/translate-a64.c: Correct unallocated checks for ldst_excl (2015-11-24 14:12:15 +0000)

----------------------------------------------------------------
target-arm queue:
 * fix minimum RAM check warning on xlnx-ep108
 * remove unused define from aarch64-linux-user.mak config
 * don't mask out bits [47:40] in ARMv8 LPAE descriptors
 * correct unallocated instruction checks for ldst_excl

----------------------------------------------------------------
Alistair Francis (1):
      xlnx-ep108: Fix minimum RAM check

Peter Maydell (3):
      default-configs/aarch64-linux-user.mak: Remove unused define
      target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
      target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

 default-configs/aarch64-linux-user.mak |  2 --
 hw/arm/xlnx-ep108.c                    |  2 +-
 target-arm/helper.c                    | 12 +++++++++++-
 target-arm/translate-a64.c             | 15 ++-------------
 4 files changed, 14 insertions(+), 17 deletions(-)

[Qemu-devel] [PULL 1/4] xlnx-ep108: Fix minimum RAM check

[Peter Maydell]

From: Alistair Francis <alistair.francis@xilinx.com>

The minimum RAM check logic for the Xiilnx EP108 was off by one,
which caused a false positive. Correct the logic to only print
warnings when the RAM is below 0x8000000.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: fba8112ca7b01efd72553332b8045ecf107b7662.1448021100.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/xlnx-ep108.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c
index 2899698..85b978f 100644
--- a/hw/arm/xlnx-ep108.c
+++ b/hw/arm/xlnx-ep108.c
@@ -51,7 +51,7 @@ static void xlnx_ep108_init(MachineState *machine)
         machine->ram_size = EP108_MAX_RAM_SIZE;
     }
 
-    if (machine->ram_size <= 0x08000000) {
+    if (machine->ram_size < 0x08000000) {
         qemu_log("WARNING: RAM size " RAM_ADDR_FMT " is small for EP108",
                  machine->ram_size);
     }
-- 
1.9.1

[Qemu-devel] [PULL 2/4] default-configs/aarch64-linux-user.mak: Remove unused define

[Peter Maydell]

The uses of the CONFIG_GDBSTUB_XML define were removed in commit
b77abd95a9484c, but the define in aarch64-linux-user.mak somehow
escaped the cull (the patchset probably crossed in the mail with
the patches adding aarch64 support). Remove the stray define.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 1447690178-4560-1-git-send-email-peter.maydell@linaro.org
---
 default-configs/aarch64-linux-user.mak | 2 --
 1 file changed, 2 deletions(-)

diff --git a/default-configs/aarch64-linux-user.mak b/default-configs/aarch64-linux-user.mak
index 3df7de5..0a5b08a 100644
--- a/default-configs/aarch64-linux-user.mak
+++ b/default-configs/aarch64-linux-user.mak
@@ -1,3 +1 @@
 # Default configuration for aarch64-linux-user
-
-CONFIG_GDBSTUB_XML=y
-- 
1.9.1

[Qemu-devel] [PULL 3/4] target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8

[Peter Maydell]

In an LPAE format descriptor in ARMv8 the address field extends
up to bit 47, not just bit 39. Correct the masking so we don't
give incorrect results if the output address size is greater
than 40 bits, as it can be for AArch64.

(Note that we don't yet support the new-in-v8 Address Size fault which
should be generated if any translation table entry or TTBR contains
an address with non-zero bits above the most significant bit of the
maximum output address size.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1448029971-9875-1-git-send-email-peter.maydell@linaro.org
---
 target-arm/helper.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4ecae61..afc4163 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6642,6 +6642,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
     int ap, ns, xn, pxn;
     uint32_t el = regime_el(env, mmu_idx);
     bool ttbr1_valid = true;
+    uint64_t descaddrmask;
 
     /* TODO:
      * This code does not handle the different format TCR for VTCR_EL2.
@@ -6831,6 +6832,15 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
     descaddr = extract64(ttbr, 0, 48);
     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
 
+    /* The address field in the descriptor goes up to bit 39 for ARMv7
+     * but up to bit 47 for ARMv8.
+     */
+    if (arm_feature(env, ARM_FEATURE_V8)) {
+        descaddrmask = 0xfffffffff000ULL;
+    } else {
+        descaddrmask = 0xfffffff000ULL;
+    }
+
     /* Secure accesses start with the page table in secure memory and
      * can be downgraded to non-secure at any step. Non-secure accesses
      * remain non-secure. We implement this by just ORing in the NSTable/NS
@@ -6854,7 +6864,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
             /* Invalid, or the Reserved level 3 encoding */
             goto do_fault;
         }
-        descaddr = descriptor & 0xfffffff000ULL;
+        descaddr = descriptor & descaddrmask;
 
         if ((descriptor & 2) && (level < 3)) {
             /* Table entry. The top five bits are attributes which  may
-- 
1.9.1

[Qemu-devel] [PULL 4/4] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

[Peter Maydell]

The checks for the unallocated encodings in the ldst_excl group
(exclusives and load-acquire/store-release) were not correct. This
error meant that in turn we ended up with code attempting to handle
the non-existent case of "non-exclusive load-acquire/store-release
pair". Delete that broken and now unreachable code.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
---
 target-arm/translate-a64.c | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index fe485a4..14e8131 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
  *  o2: 0 -> exclusive, 1 -> not
  *  o1: 0 -> single register, 1 -> register pair
  *  o0: 1 -> load-acquire/store-release, 0 -> not
- *
- *  o0 == 0 AND o2 == 1 is un-allocated
- *  o1 == 1 is un-allocated except for 32 and 64 bit sizes
  */
 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
 {
@@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
     int size = extract32(insn, 30, 2);
     TCGv_i64 tcg_addr;
 
-    if ((!is_excl && !is_lasr) ||
+    if ((!is_excl && !is_pair && !is_lasr) ||
+        (!is_excl && is_pair) ||
         (is_pair && size < 2)) {
         unallocated_encoding(s);
         return;
@@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
         } else {
             do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false);
         }
-        if (is_pair) {
-            TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
-            tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
-            if (is_store) {
-                do_gpr_st(s, tcg_rt2, tcg_addr, size);
-            } else {
-                do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false);
-            }
-        }
     }
 }
 
-- 
1.9.1

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 24 November 2015 at 14:18, Peter Maydell <peter.maydell@linaro.org> wrote:
> A handful of minor ARM bugfixes...
>
> thanks
> -- PMM
>
> The following changes since commit 229c0372cf3ca201c41d2bb121627e6752e776ad:
>
>   Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging (2015-11-24 10:27:19 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151124
>
> for you to fetch changes up to e14f0eb12f920fd96b9f79d15cedd437648e8667:
>
>   target-arm/translate-a64.c: Correct unallocated checks for ldst_excl (2015-11-24 14:12:15 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * fix minimum RAM check warning on xlnx-ep108
>  * remove unused define from aarch64-linux-user.mak config
>  * don't mask out bits [47:40] in ARMv8 LPAE descriptors
>  * correct unallocated instruction checks for ldst_excl
>
> ----------------------------------------------------------------
> Alistair Francis (1):
>       xlnx-ep108: Fix minimum RAM check
>
> Peter Maydell (3):
>       default-configs/aarch64-linux-user.mak: Remove unused define
>       target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8
>       target-arm/translate-a64.c: Correct unallocated checks for ldst_excl

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A last handful of patches before the rc0. These are all bugfixes
so they could equally well go into rc1, but since my pullreq
queue is otherwise empty I might as well push them out. The
FPSCR bugfix is definitely one I'd like in rc0; the rest are
not really user-visible I think.

thanks
-- PMM

The following changes since commit c4107e8208d0222f9b328691b519aaee4101db87:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-07-08 10:26:18 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190708

for you to fetch changes up to 85795187f416326f87177cabc39fae1911f04c50:

  target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR (2019-07-08 14:11:31 +0100)

----------------------------------------------------------------
target-arm queue:
 * tests/migration-test: Fix read off end of aarch64_kernel array
 * Fix sve_zcr_len_for_el off-by-one error
 * hw/arm/sbsa-ref: Silence Coverity nit
 * vfp_helper: Call set_fpscr_to_host before updating to FPSCR

----------------------------------------------------------------
Peter Maydell (2):
      tests/migration-test: Fix read off end of aarch64_kernel array
      hw/arm/sbsa-ref: Remove unnecessary check for secure_sysmem == NULL

Philippe Mathieu-Daudé (1):
      target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR

Richard Henderson (1):
      target/arm: Fix sve_zcr_len_for_el

 hw/arm/sbsa-ref.c       |  8 ++------
 target/arm/helper.c     |  4 ++--
 target/arm/vfp_helper.c |  4 ++--
 tests/migration-test.c  | 22 +++++++---------------
 4 files changed, 13 insertions(+), 25 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On Mon, 8 Jul 2019 at 14:22, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> A last handful of patches before the rc0. These are all bugfixes
> so they could equally well go into rc1, but since my pullreq
> queue is otherwise empty I might as well push them out. The
> FPSCR bugfix is definitely one I'd like in rc0; the rest are
> not really user-visible I think.
>
> thanks
> -- PMM
>
> The following changes since commit c4107e8208d0222f9b328691b519aaee4101db87:
>
>   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-07-08 10:26:18 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190708
>
> for you to fetch changes up to 85795187f416326f87177cabc39fae1911f04c50:
>
>   target/arm/vfp_helper: Call set_fpscr_to_host before updating to FPSCR (2019-07-08 14:11:31 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * tests/migration-test: Fix read off end of aarch64_kernel array
>  * Fix sve_zcr_len_for_el off-by-one error
>  * hw/arm/sbsa-ref: Silence Coverity nit
>  * vfp_helper: Call set_fpscr_to_host before updating to FPSCR


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.

-- PMM

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190708132237.7911-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20190708132237.7911-1-peter.maydell@linaro.org
Type: series
Subject: [Qemu-devel] [PULL 0/4] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 t [tag update]            patchew/20190708132237.7911-1-peter.maydell@linaro.org -> patchew/20190708132237.7911-1-peter.maydell@linaro.org
Switched to a new branch 'test'

=== OUTPUT BEGIN ===
checkpatch.pl: no revisions returned for revlist '1'
=== OUTPUT END ===

Test command exited with code: 255


The full log is available at
http://patchew.org/logs/20190708132237.7911-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

ARM queue, mostly bug fixes to go into rc0.
The integratorcp and fsl_imx* changes are migration
compat breakers but that's ok for these boards.

thanks
-- PMM


The following changes since commit ce1d20aac8533357650774c2c240e30de87dc122:

  Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-24' into staging (2017-07-24 16:20:47 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170724

for you to fetch changes up to b2d1b0507d1b80f23da12dd8aab56944fe380a09:

  integratorcp: Don't migrate flash using vmstate_register_ram_global() (2017-07-24 17:59:28 +0100)

----------------------------------------------------------------
target-arm queue:
 * fix a TCG temporary leak in aarch64 rev16
 * fsl_imx*: migrate the ROM contents
 * integratorcp: don't use vmstate_register_ram_global for flash
 * mps2: Correctly set parent bus for SCC device

----------------------------------------------------------------
Emilio G. Cota (1):
      target/arm: fix TCG temp leak in aarch64 rev16

Peter Maydell (3):
      fsl_imx*: Migrate ROM contents
      mps2: Correctly set parent bus for SCC device
      integratorcp: Don't migrate flash using vmstate_register_ram_global()

 hw/arm/fsl-imx25.c         | 4 ++--
 hw/arm/fsl-imx31.c         | 4 ++--
 hw/arm/fsl-imx6.c          | 4 ++--
 hw/arm/integratorcp.c      | 3 +--
 hw/arm/mps2.c              | 2 +-
 target/arm/translate-a64.c | 1 +
 6 files changed, 9 insertions(+), 9 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 24 July 2017 at 18:06, Peter Maydell <peter.maydell@linaro.org> wrote:
> ARM queue, mostly bug fixes to go into rc0.
> The integratorcp and fsl_imx* changes are migration
> compat breakers but that's ok for these boards.
>
> thanks
> -- PMM
>
>
> The following changes since commit ce1d20aac8533357650774c2c240e30de87dc122:
>
>   Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-24' into staging (2017-07-24 16:20:47 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170724
>
> for you to fetch changes up to b2d1b0507d1b80f23da12dd8aab56944fe380a09:
>
>   integratorcp: Don't migrate flash using vmstate_register_ram_global() (2017-07-24 17:59:28 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * fix a TCG temporary leak in aarch64 rev16
>  * fsl_imx*: migrate the ROM contents
>  * integratorcp: don't use vmstate_register_ram_global for flash
>  * mps2: Correctly set parent bus for SCC device
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

A surprisingly short target-arm queue, but no point in holding
onto these waiting for more code to arrive :-)

thanks
-- PMM

The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:

  Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711

for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:

  target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)

----------------------------------------------------------------
target-arm queue:
 * v7M: ignore writes to CONTROL.SPSEL from Thread mode
 * KVM: Enable in-kernel timers with user space gic
 * aspeed: Register all watchdogs
 * hw/misc: Add Exynos4210 Pseudo Random Number Generator

----------------------------------------------------------------
Alexander Graf (1):
      ARM: KVM: Enable in-kernel timers with user space gic

Joel Stanley (1):
      aspeed: Register all watchdogs

Krzysztof Kozlowski (1):
      hw/misc: Add Exynos4210 Pseudo Random Number Generator

Peter Maydell (1):
      target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode

 hw/misc/Makefile.objs       |   2 +-
 include/hw/arm/aspeed_soc.h |   4 +-
 include/sysemu/kvm.h        |  11 ++
 target/arm/cpu.h            |   3 +
 accel/kvm/kvm-all.c         |   5 +
 accel/stubs/kvm-stub.c      |   5 +
 hw/arm/aspeed_soc.c         |  25 ++--
 hw/arm/exynos4210.c         |   4 +
 hw/intc/arm_gic.c           |   7 ++
 hw/misc/exynos4210_rng.c    | 277 ++++++++++++++++++++++++++++++++++++++++++++
 target/arm/helper.c         |  13 ++-
 target/arm/kvm.c            |  51 ++++++++
 12 files changed, 394 insertions(+), 13 deletions(-)
 create mode 100644 hw/misc/exynos4210_rng.c

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

On 11 July 2017 at 11:29, Peter Maydell <peter.maydell@linaro.org> wrote:
> A surprisingly short target-arm queue, but no point in holding
> onto these waiting for more code to arrive :-)
>
> thanks
> -- PMM
>
> The following changes since commit 3d0bf8dfdfebd7f2ae41b6f220444b8047d6b1ee:
>
>   Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170710a' into staging (2017-07-10 18:13:03 +0100)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20170711
>
> for you to fetch changes up to 792dac309c8660306557ba058b8b5a6a75ab3c1f:
>
>   target-arm: v7M: ignore writes to CONTROL.SPSEL from Thread mode (2017-07-11 11:21:26 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * v7M: ignore writes to CONTROL.SPSEL from Thread mode
>  * KVM: Enable in-kernel timers with user space gic
>  * aspeed: Register all watchdogs
>  * hw/misc: Add Exynos4210 Pseudo Random Number Generator
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

Hi; here's the last target-arm pull request before I
go off on holiday -- four fairly minor bug fixes.
Hopefully it merges without problems, because I won't
be around tomorrow to do a respin :-)

thanks
-- PMM

The following changes since commit 9226682a401f34b10fd79dfe17ba334da0800747:

  Merge remote-tracking branch 'sstabellini/tags/xen-20161102-tag' into staging (2016-11-04 09:26:24 +0000)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161107

for you to fetch changes up to 9706e0162d2405218fd7376ffdf13baed8569a4b:

  hw/i2c/bitbang_i2c: Handle NACKs from devices (2016-11-07 10:01:15 +0000)

----------------------------------------------------------------
target-arm queue:
 * bitbang_i2c: Handle NACKs from devices
 * Fix corruption of CPSR when SCTLR.EE is set
 * nvic: set pending status for not active interrupts
 * char: cadence: check baud rate generator and divider values

----------------------------------------------------------------
Julian Brown (1):
      Fix corruption of CPSR when SCTLR.EE is set

Marcin Krzeminski (1):
      nvic: set pending status for not active interrupts

Peter Maydell (1):
      hw/i2c/bitbang_i2c: Handle NACKs from devices

Prasad J Pandit (1):
      char: cadence: check baud rate generator and divider values

 hw/char/cadence_uart.c | 15 +++++++++++++++
 hw/i2c/bitbang_i2c.c   | 19 +++++++++++++++----
 hw/intc/arm_gic.c      | 22 ++++++++++++++++++++--
 target-arm/helper.c    |  2 +-
 4 files changed, 51 insertions(+), 7 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Stefan Hajnoczi]

[-- Attachment #1: Type: text/plain, Size: 1865 bytes --]

On Mon, Nov 07, 2016 at 10:47:29AM +0000, Peter Maydell wrote:
> Hi; here's the last target-arm pull request before I
> go off on holiday -- four fairly minor bug fixes.
> Hopefully it merges without problems, because I won't
> be around tomorrow to do a respin :-)
> 
> thanks
> -- PMM
> 
> The following changes since commit 9226682a401f34b10fd79dfe17ba334da0800747:
> 
>   Merge remote-tracking branch 'sstabellini/tags/xen-20161102-tag' into staging (2016-11-04 09:26:24 +0000)
> 
> are available in the git repository at:
> 
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20161107
> 
> for you to fetch changes up to 9706e0162d2405218fd7376ffdf13baed8569a4b:
> 
>   hw/i2c/bitbang_i2c: Handle NACKs from devices (2016-11-07 10:01:15 +0000)
> 
> ----------------------------------------------------------------
> target-arm queue:
>  * bitbang_i2c: Handle NACKs from devices
>  * Fix corruption of CPSR when SCTLR.EE is set
>  * nvic: set pending status for not active interrupts
>  * char: cadence: check baud rate generator and divider values
> 
> ----------------------------------------------------------------
> Julian Brown (1):
>       Fix corruption of CPSR when SCTLR.EE is set
> 
> Marcin Krzeminski (1):
>       nvic: set pending status for not active interrupts
> 
> Peter Maydell (1):
>       hw/i2c/bitbang_i2c: Handle NACKs from devices
> 
> Prasad J Pandit (1):
>       char: cadence: check baud rate generator and divider values
> 
>  hw/char/cadence_uart.c | 15 +++++++++++++++
>  hw/i2c/bitbang_i2c.c   | 19 +++++++++++++++----
>  hw/intc/arm_gic.c      | 22 ++++++++++++++++++++--
>  target-arm/helper.c    |  2 +-
>  4 files changed, 51 insertions(+), 7 deletions(-)

Thanks, applied to my staging tree:
https://github.com/stefanha/qemu/commits/staging

Stefan

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[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

target-arm pullreq, containing a fix for a dumb SRS bug I
introduced, and the update to migration to use vmstate
(both of which have been on the list since before freeze).
Please pull.

thanks
-- PMM

The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:

  configure: remove duplicate test (2013-04-18 14:12:31 +0200)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next

for you to fetch changes up to e91f229a253f489f6d12b946ad7bdcdc158c5b67:

  target-arm: Correctly restore FPSCR (2013-04-19 12:24:19 +0100)

----------------------------------------------------------------
Juan Quintela (1):
      target-arm: port ARM CPU save/load to use VMState

Peter Chubb (1):
      target-arm: Reinsert missing return statement in ARM mode SRS decode

Peter Maydell (2):
      target-arm: Add some missing CPU state fields to VMState
      target-arm: Correctly restore FPSCR

 target-arm/cpu-qom.h   |    4 +
 target-arm/cpu.c       |    1 +
 target-arm/cpu.h       |    2 -
 target-arm/machine.c   |  430 ++++++++++++++++++++++++------------------------
 target-arm/translate.c |    1 +
 5 files changed, 222 insertions(+), 216 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Blue Swirl]

Thanks, pulled.

On Fri, Apr 19, 2013 at 3:06 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm pullreq, containing a fix for a dumb SRS bug I
> introduced, and the update to migration to use vmstate
> (both of which have been on the list since before freeze).
> Please pull.
>
> thanks
> -- PMM
>
> The following changes since commit 09dada400328d75daf79e3eca1e48e024fec148d:
>
>   configure: remove duplicate test (2013-04-18 14:12:31 +0200)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.next
>
> for you to fetch changes up to e91f229a253f489f6d12b946ad7bdcdc158c5b67:
>
>   target-arm: Correctly restore FPSCR (2013-04-19 12:24:19 +0100)
>
> ----------------------------------------------------------------
> Juan Quintela (1):
>       target-arm: port ARM CPU save/load to use VMState
>
> Peter Chubb (1):
>       target-arm: Reinsert missing return statement in ARM mode SRS decode
>
> Peter Maydell (2):
>       target-arm: Add some missing CPU state fields to VMState
>       target-arm: Correctly restore FPSCR
>
>  target-arm/cpu-qom.h   |    4 +
>  target-arm/cpu.c       |    1 +
>  target-arm/cpu.h       |    2 -
>  target-arm/machine.c   |  430 ++++++++++++++++++++++++------------------------
>  target-arm/translate.c |    1 +
>  5 files changed, 222 insertions(+), 216 deletions(-)

[Qemu-devel] [PULL 0/4] target-arm queue

[Peter Maydell]

Hi; this is a pullreq for the current target-arm queue. Some
minor tweaks and the patch which handles get/put_user() failure
in the semihosting code. Please pull.

thanks
-- PMM

The following changes since commit a8170e5e97ad17ca169c64ba87ae2f53850dab4c:

  Rename target_phys_addr_t to hwaddr (2012-10-23 08:58:25 -0500)

are available in the git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

for you to fetch changes up to 8b279a60dc3ca53923701dfec6e54bea9d13cfb7:

  target-arm: Remove out of date FIXME regarding saturating arithmetic (2012-10-24 13:33:29 +0100)

----------------------------------------------------------------
Peter Maydell (4):
      arm-semi.c: Handle get/put_user() failure accessing arguments
      target-arm: Use TCG operation for Neon 64 bit negation
      target-arm: Implement abs_i32 inline rather than as a helper
      target-arm: Remove out of date FIXME regarding saturating arithmetic

 target-arm/arm-semi.c    |  167 +++++++++++++++++++++++++++++-----------------
 target-arm/helper.c      |    5 --
 target-arm/helper.h      |    2 -
 target-arm/neon_helper.c |    6 --
 target-arm/op_helper.c   |    2 -
 target-arm/translate.c   |   15 ++++-
 6 files changed, 118 insertions(+), 79 deletions(-)

Re: [Qemu-devel] [PULL 0/4] target-arm queue

[Blue Swirl]

On Wed, Oct 24, 2012 at 1:02 PM, Peter Maydell <peter.maydell@linaro.org> wrote:
> Hi; this is a pullreq for the current target-arm queue. Some
> minor tweaks and the patch which handles get/put_user() failure
> in the semihosting code. Please pull.

Thanks, pulled.

>
> thanks
> -- PMM
>
> The following changes since commit a8170e5e97ad17ca169c64ba87ae2f53850dab4c:
>
>   Rename target_phys_addr_t to hwaddr (2012-10-23 08:58:25 -0500)
>
> are available in the git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream
>
> for you to fetch changes up to 8b279a60dc3ca53923701dfec6e54bea9d13cfb7:
>
>   target-arm: Remove out of date FIXME regarding saturating arithmetic (2012-10-24 13:33:29 +0100)
>
> ----------------------------------------------------------------
> Peter Maydell (4):
>       arm-semi.c: Handle get/put_user() failure accessing arguments
>       target-arm: Use TCG operation for Neon 64 bit negation
>       target-arm: Implement abs_i32 inline rather than as a helper
>       target-arm: Remove out of date FIXME regarding saturating arithmetic
>
>  target-arm/arm-semi.c    |  167 +++++++++++++++++++++++++++++-----------------
>  target-arm/helper.c      |    5 --
>  target-arm/helper.h      |    2 -
>  target-arm/neon_helper.c |    6 --
>  target-arm/op_helper.c   |    2 -
>  target-arm/translate.c   |   15 ++++-
>  6 files changed, 118 insertions(+), 79 deletions(-)