[Qemu-devel] [PULL 0/2] target-mips queue

[Qemu-devel] [PULL 0/2] target-mips queue

[Leon Alrae]

Hi,

Just a couple of MIPS64 64-bit addressing bug fixes for 2.5-rc2.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit 5522a841cab5f15ac0f8d207b320c21755a7a1a5:

  Merge remote-tracking branch 'remotes/ehabkost/tags/numa-pull-request' into staging (2015-11-23 16:07:49 +0000)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20151124

for you to fetch changes up to f93c3a8d0c0c1038dbe1e957eb8ab92671137975:

  target-mips: flush QEMU TLB when disabling 64-bit addressing (2015-11-24 11:01:03 +0000)

----------------------------------------------------------------
MIPS patches 2015-11-24

Changes:
* bugfixes for accessing 64-bit addresses

----------------------------------------------------------------
James Hogan (1):
      target-mips: Fix exceptions while UX=0

Leon Alrae (1):
      target-mips: flush QEMU TLB when disabling 64-bit addressing

 target-mips/cpu.h       | 18 +++++++++++++++++-
 target-mips/helper.c    | 12 ++++++++++++
 target-mips/op_helper.c | 13 -------------
 3 files changed, 29 insertions(+), 14 deletions(-)

[Qemu-devel] [PULL 1/2] target-mips: Fix exceptions while UX=0

[Leon Alrae]

From: James Hogan <james.hogan@imgtec.com>

Commit 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit address
wrapping") added a new hflag MIPS_HFLAG_AWRAP, which indicates that
64-bit addressing is disallowed in the current mode, so hflag users
don't need to worry about the complexities of working that out, for
example checking both MIPS_HFLAG_KSU and MIPS_HFLAG_UX.

However when exceptions are taken outside of exception level,
mips_cpu_do_interrupt() manipulates the env->hflags directly rather than
using compute_hflags() to update them, and this code wasn't updated
accordingly. As a result, when UX is cleared, MIPS_HFLAG_AWRAP is set,
but it doesn't get cleared on entry back into kernel mode due to an
exception. Kernel mode then cannot access the 64-bit segments resulting
in a nested exception loop. The same applies to errors and debug
exceptions.

Fix by updating mips_cpu_do_interrupt() to clear the MIPS_HFLAG_WRAP
flag when necessary, according to compute_hflags().

Fixes: 01f728857941 ("target-mips: Status.UX/SX/KX enable 32-bit...")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Leon Alrae <leon.alrae@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/helper.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/target-mips/helper.c b/target-mips/helper.c
index b3fe816..118072a 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -524,6 +524,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
  enter_debug_mode:
         if (env->insn_flags & ISA_MIPS3) {
             env->hflags |= MIPS_HFLAG_64;
+            if (!(env->insn_flags & ISA_MIPS64R6) ||
+                env->CP0_Status & (1 << CP0St_KX)) {
+                env->hflags &= ~MIPS_HFLAG_AWRAP;
+            }
         }
         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
         env->hflags &= ~(MIPS_HFLAG_KSU);
@@ -548,6 +552,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
         if (env->insn_flags & ISA_MIPS3) {
             env->hflags |= MIPS_HFLAG_64;
+            if (!(env->insn_flags & ISA_MIPS64R6) ||
+                env->CP0_Status & (1 << CP0St_KX)) {
+                env->hflags &= ~MIPS_HFLAG_AWRAP;
+            }
         }
         env->hflags |= MIPS_HFLAG_CP0;
         env->hflags &= ~(MIPS_HFLAG_KSU);
@@ -725,6 +733,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
             env->CP0_Status |= (1 << CP0St_EXL);
             if (env->insn_flags & ISA_MIPS3) {
                 env->hflags |= MIPS_HFLAG_64;
+                if (!(env->insn_flags & ISA_MIPS64R6) ||
+                    env->CP0_Status & (1 << CP0St_KX)) {
+                    env->hflags &= ~MIPS_HFLAG_AWRAP;
+                }
             }
             env->hflags |= MIPS_HFLAG_CP0;
             env->hflags &= ~(MIPS_HFLAG_KSU);
-- 
2.1.0

[Qemu-devel] [PULL 2/2] target-mips: flush QEMU TLB when disabling 64-bit addressing

[Leon Alrae]

CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit
Kernel/Supervisor/User Segments. If bit is cleared an access to
corresponding segment should generate Address Error Exception.

However, the guest may still be able to access some pages belonging to
the disabled 64-bit segment because we forget to flush QEMU TLB.

This patch fixes it.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/cpu.h       | 18 +++++++++++++++++-
 target-mips/op_helper.c | 13 -------------
 2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index fa919c1..89c01f7 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -961,6 +961,15 @@ static inline void compute_hflags(CPUMIPSState *env)
 }
 
 #ifndef CONFIG_USER_ONLY
+static inline void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
+{
+    MIPSCPU *cpu = mips_env_get_cpu(env);
+
+    /* Flush qemu's TLB and discard all shadowed entries.  */
+    tlb_flush(CPU(cpu), flush_global);
+    env->tlb->tlb_in_use = env->tlb->nb_tlb;
+}
+
 /* Called for updates to CP0_Status.  */
 static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 {
@@ -999,6 +1008,7 @@ static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
 {
     uint32_t mask = env->CP0_Status_rw_bitmask;
+    target_ulong old = env->CP0_Status;
 
     if (env->insn_flags & ISA_MIPS32R6) {
         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
@@ -1014,7 +1024,13 @@ static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
     }
 
-    env->CP0_Status = (env->CP0_Status & ~mask) | (val & mask);
+    env->CP0_Status = (old & ~mask) | (val & mask);
+#if defined(TARGET_MIPS64)
+    if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
+        /* Access to at least one of the 64-bit segments has been disabled */
+        cpu_mips_tlb_flush(env, 1);
+    }
+#endif
     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
         sync_c0_status(env, env, env->current_tc);
     } else {
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 056d53b..d2c98c9 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -23,10 +23,6 @@
 #include "exec/cpu_ldst.h"
 #include "sysemu/kvm.h"
 
-#ifndef CONFIG_USER_ONLY
-static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
-#endif
-
 /*****************************************************************************/
 /* Exceptions processing helpers */
 
@@ -1846,15 +1842,6 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
 
 #ifndef CONFIG_USER_ONLY
 /* TLB management */
-static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
-{
-    MIPSCPU *cpu = mips_env_get_cpu(env);
-
-    /* Flush qemu's TLB and discard all shadowed entries.  */
-    tlb_flush(CPU(cpu), flush_global);
-    env->tlb->tlb_in_use = env->tlb->nb_tlb;
-}
-
 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
 {
     /* Discard entries from env->tlb[first] onwards.  */
-- 
2.1.0

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 24 November 2015 at 16:59, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> Just a couple of MIPS64 64-bit addressing bug fixes for 2.5-rc2.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit 5522a841cab5f15ac0f8d207b320c21755a7a1a5:
>
>   Merge remote-tracking branch 'remotes/ehabkost/tags/numa-pull-request' into staging (2015-11-23 16:07:49 +0000)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20151124
>
> for you to fetch changes up to f93c3a8d0c0c1038dbe1e957eb8ab92671137975:
>
>   target-mips: flush QEMU TLB when disabling 64-bit addressing (2015-11-24 11:01:03 +0000)
>
> ----------------------------------------------------------------
> MIPS patches 2015-11-24
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/2] target-mips queue

[Yongbok Kim]

The following changes since commit 871a0f7ad2b9560c5f7d640125c5be95ca23ca7f:

  Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170728' into staging (2017-07-28 10:35:02 +0100)

are available in the git repository at:

  git://github.com/yongbok/upstream-qemu.git tags/mips-20170728

for you to fetch changes up to 665df9010aa40d1e028d6ad5d3bdb4d9b0a3294c:

  Revert "elf-loader: warn about invalid endianness" (2017-07-28 13:32:32 +0100)

----------------------------------------------------------------
MIPS patches 2017-07-28

Changes:
* Improve ths MIPS board kernel load error reporting
* Revert unnecessary warning messages

----------------------------------------------------------------

Alexey Kardashevskiy (1):
  Revert "elf-loader: warn about invalid endianness"

Aurelien Jarno (1):
  hw/mips: load_elf_strerror to report kernel loading failure

 hw/core/loader.c        |  1 -
 hw/mips/mips_fulong2e.c | 15 +++++++++------
 hw/mips/mips_malta.c    | 14 ++++++++------
 hw/mips/mips_mipssim.c  |  5 +++--
 hw/mips/mips_r4k.c      |  6 ++++--
 5 files changed, 24 insertions(+), 17 deletions(-)

-- 
2.7.4

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 28 July 2017 at 14:07, Yongbok Kim <yongbok.kim@imgtec.com> wrote:
> The following changes since commit 871a0f7ad2b9560c5f7d640125c5be95ca23ca7f:
>
>   Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170728' into staging (2017-07-28 10:35:02 +0100)
>
> are available in the git repository at:
>
>   git://github.com/yongbok/upstream-qemu.git tags/mips-20170728
>
> for you to fetch changes up to 665df9010aa40d1e028d6ad5d3bdb4d9b0a3294c:
>
>   Revert "elf-loader: warn about invalid endianness" (2017-07-28 13:32:32 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2017-07-28
>
> Changes:
> * Improve ths MIPS board kernel load error reporting
> * Revert unnecessary warning messages
>
> ----------------------------------------------------------------
>
> Alexey Kardashevskiy (1):
>   Revert "elf-loader: warn about invalid endianness"
>
> Aurelien Jarno (1):
>   hw/mips: load_elf_strerror to report kernel loading failure
>

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/2] target-mips queue

[Yongbok Kim]

The following changes since commit b5ed2e11ef39a308dcbef46f66774557b4a41fce:

  build: disable Xen on ARM (2017-07-11 11:23:47 +0100)

are available in the git repository at:

  git://github.com/yongbok/upstream-qemu.git tags/mips-20170711

for you to fetch changes up to 9768e2abf7ca3ef181f7cec134d7305c1643f78a:

  mips/malta: load the initrd at the end of the low memory (2017-07-11 15:06:34 +0100)

----------------------------------------------------------------
MIPS patches 2017-07-11

Changes:
* Fix MSA copy_[s|u]_df corner case of rd = 0
* Update malta to load the initrd at the end of the low memory

----------------------------------------------------------------

Aurelien Jarno (1):
  mips/malta: load the initrd at the end of the low memory

Miodrag Dinic (1):
  target/mips: fix msa copy_[s|u]_df rd = 0 corner case

 hw/mips/mips_malta.c    | 5 +++--
 target/mips/translate.c | 8 ++++++--
 2 files changed, 9 insertions(+), 4 deletions(-)

-- 
2.7.4

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 11 July 2017 at 16:16, Yongbok Kim <yongbok.kim@imgtec.com> wrote:
> The following changes since commit b5ed2e11ef39a308dcbef46f66774557b4a41fce:
>
>   build: disable Xen on ARM (2017-07-11 11:23:47 +0100)
>
> are available in the git repository at:
>
>   git://github.com/yongbok/upstream-qemu.git tags/mips-20170711
>
> for you to fetch changes up to 9768e2abf7ca3ef181f7cec134d7305c1643f78a:
>
>   mips/malta: load the initrd at the end of the low memory (2017-07-11 15:06:34 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2017-07-11
>
> Changes:
> * Fix MSA copy_[s|u]_df corner case of rd = 0
> * Update malta to load the initrd at the end of the low memory
>
> ----------------------------------------------------------------
>
> Aurelien Jarno (1):
>   mips/malta: load the initrd at the end of the low memory
>
> Miodrag Dinic (1):
>   target/mips: fix msa copy_[s|u]_df rd = 0 corner case
>
>  hw/mips/mips_malta.c    | 5 +++--
>  target/mips/translate.c | 8 ++++++--
>  2 files changed, 9 insertions(+), 4 deletions(-)

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/2] target-mips queue

[Yongbok Kim]

The following changes since commit 10f25e4844cb9b3f02fb032f88051dd5b65b4206:

  Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170222' into staging (2017-02-23 09:59:40 +0000)

are available in the git repository at:

  git://github.com/yongbok/upstream-qemu.git tags/mips-20170224

for you to fetch changes up to 0288d4485392832b25e40551433377a36d56dd8c:

  hw/mips: MIPS Boston board support (2017-02-24 00:04:32 +0000)

----------------------------------------------------------------
MIPS patches 2017-02-24

Changes:
* Revert the boston model commit which breaks "make check" on 32-bit hosts
* Add the boston model with fixing the issue.

----------------------------------------------------------------

Paul Burton (1):
  hw/mips: MIPS Boston board support

Yongbok Kim (1):
  Revert "hw/mips: MIPS Boston board support"

 hw/mips/boston.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.7.4

[Qemu-devel] [PULL 0/2] target-mips queue

[Yongbok Kim]

Hi, 

This is my first pull-req for MIPS.

Thanks,
Yongbok

The following changes since commit c640f2849ee8775fe1bbd7a2772610aa77816f9f:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2016-09-28 23:02:56 +0100)

are available in the git repository at:

  git://github.com/yongbok/upstream-qemu.git tags/mips-20160929

for you to fetch changes up to 73bfa8c0e0295df92d5fe61e0149db7b36cdc0c4:

  hw/dma: vmstateify rc4030 (2016-09-29 12:07:51 +0100)

----------------------------------------------------------------
MIPS patches 2016-09-29

Changes:
* MIPS Maintainer update
* vmstateify rc4030

----------------------------------------------------------------
Dr. David Alan Gilbert (1):
      hw/dma: vmstateify rc4030

Leon Alrae (1):
      MAINTAINERS: update target-mips maintainers

 MAINTAINERS     |  2 +-
 hw/dma/rc4030.c | 81 +++++++++++++++++++--------------------------------------
 2 files changed, 28 insertions(+), 55 deletions(-)

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 29 September 2016 at 06:19, Yongbok Kim <yongbok.kim@imgtec.com> wrote:
> Hi,
>
> This is my first pull-req for MIPS.
>
> Thanks,
> Yongbok
>
> The following changes since commit c640f2849ee8775fe1bbd7a2772610aa77816f9f:
>
>   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2016-09-28 23:02:56 +0100)
>
> are available in the git repository at:
>
>   git://github.com/yongbok/upstream-qemu.git tags/mips-20160929
>
> for you to fetch changes up to 73bfa8c0e0295df92d5fe61e0149db7b36cdc0c4:
>
>   hw/dma: vmstateify rc4030 (2016-09-29 12:07:51 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2016-09-29
>
> Changes:
> * MIPS Maintainer update
> * vmstateify rc4030

Your GPG key hasn't been signed by anybody -- are you in a position
to get it signed by somebody else who can in-person verify your identity
(eg Leon)?

thanks
-- PMM

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Yongbok Kim]

> 
> Your GPG key hasn't been signed by anybody -- are you in a position
> to get it signed by somebody else who can in-person verify your identity
> (eg Leon)?
> 
> thanks
> -- PMM
> 

Hi Peter,

We have just arranged the key signing and Leon has signed my key.

Thanks,
Yongbok

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 30 September 2016 at 01:16, Yongbok Kim <yongbok.kim@imgtec.com> wrote:
>>
>> Your GPG key hasn't been signed by anybody -- are you in a position
>> to get it signed by somebody else who can in-person verify your identity
>> (eg Leon)?
>
> Hi Peter,
>
> We have just arranged the key signing and Leon has signed my key.

Thanks; I have applied the pull request to master.

-- PMM

[Qemu-devel] [PULL 0/2] target-mips queue

[Leon Alrae]

Hi,

Just a couple of bug fixes for rc1.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit 21a21b853a1bb606358af61e738abfb9aecbd720:

  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-07-27 18:18:21 +0100)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20160729

for you to fetch changes up to 701074a6fc7470d0ed54e4a4bcd4d491ad8da22e:

  target-mips: fix EntryHi.EHINV being cleared on TLB exception (2016-07-28 11:24:02 +0100)

----------------------------------------------------------------
MIPS patches 2016-07-29

Changes:
* bug fixes

----------------------------------------------------------------
Leon Alrae (1):
      target-mips: fix EntryHi.EHINV being cleared on TLB exception

Paul Burton (1):
      hw/mips_malta: Fix YAMON API print routine

 hw/mips/mips_malta.c | 2 +-
 target-mips/helper.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 29 July 2016 at 10:11, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> Just a couple of bug fixes for rc1.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit 21a21b853a1bb606358af61e738abfb9aecbd720:
>
>   Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2016-07-27 18:18:21 +0100)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20160729
>
> for you to fetch changes up to 701074a6fc7470d0ed54e4a4bcd4d491ad8da22e:
>
>   target-mips: fix EntryHi.EHINV being cleared on TLB exception (2016-07-28 11:24:02 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2016-07-29
>
> Changes:
> * bug fixes

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/2] target-mips queue

[Leon Alrae]

Hi,

Just two patches in the first target-mips pullreq for 2.7.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit bfc766d38e1fae5767d43845c15c79ac8fa6d6af:

  Update version for v2.6.0 release (2016-05-11 16:44:26 +0100)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20160513

for you to fetch changes up to 7fe91a5b33fe100bbc68ee434f947752c69b3f68:

  hw/display: QOM'ify jazz_led.c (2016-05-13 09:33:38 +0100)

----------------------------------------------------------------
MIPS patches 2016-05-13

Changes:
* fix zeroing CP0.WatchLo registers in soft reset
* QOMify Jazz led

----------------------------------------------------------------
Aurelien Jarno (1):
      target-mips: fix call to memset in soft reset code

xiaoqiang.zhao (1):
      hw/display: QOM'ify jazz_led.c

 hw/display/jazz_led.c | 18 +++++++++++-------
 target-mips/helper.c  |  2 +-
 2 files changed, 12 insertions(+), 8 deletions(-)

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 13 May 2016 at 11:44, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> Just two patches in the first target-mips pullreq for 2.7.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit bfc766d38e1fae5767d43845c15c79ac8fa6d6af:
>
>   Update version for v2.6.0 release (2016-05-11 16:44:26 +0100)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20160513
>
> for you to fetch changes up to 7fe91a5b33fe100bbc68ee434f947752c69b3f68:
>
>   hw/display: QOM'ify jazz_led.c (2016-05-13 09:33:38 +0100)
>
> ----------------------------------------------------------------
> MIPS patches 2016-05-13
>
> Changes:
> * fix zeroing CP0.WatchLo registers in soft reset
> * QOMify Jazz led
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/2] target-mips queue

[Leon Alrae]

Hi,

Just two patches for MIPS. Probably there'll be one more pullreq before
the hard-freeze adding the initial CPS support.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit ffa6564c9b13cea4b704e184d29d721f2cb061bb:

  Merge remote-tracking branch 'remotes/weil/tags/pull-wxx-20160322' into staging (2016-03-22 20:27:55 +0000)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20160323

for you to fetch changes up to b7c4ab809a4bfde4ab322b49fbe2e47536da7487:

  default-configs: add mips-softmmu-common.mak (2016-03-23 13:36:56 +0000)

----------------------------------------------------------------
MIPS patches 2016-03-23

Changes:
* add mips-softmmu-common.mak
* indicate presence of IEEE 754-2008 FPU in MIPS64R6-generic and P5600

----------------------------------------------------------------
Leon Alrae (2):
      target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs
      default-configs: add mips-softmmu-common.mak

 default-configs/mips-softmmu-common.mak | 32 ++++++++++++++++++++++++++++++++
 default-configs/mips-softmmu.mak        | 31 +------------------------------
 default-configs/mips64-softmmu.mak      | 31 +------------------------------
 default-configs/mips64el-softmmu.mak    | 31 +------------------------------
 default-configs/mipsel-softmmu.mak      | 31 +------------------------------
 target-mips/cpu.h                       |  3 +++
 target-mips/translate.c                 |  1 +
 target-mips/translate_init.c            | 22 +++++++++++++---------
 8 files changed, 53 insertions(+), 129 deletions(-)
 create mode 100644 default-configs/mips-softmmu-common.mak

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 23 March 2016 at 16:54, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> Just two patches for MIPS. Probably there'll be one more pullreq before
> the hard-freeze adding the initial CPS support.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit ffa6564c9b13cea4b704e184d29d721f2cb061bb:
>
>   Merge remote-tracking branch 'remotes/weil/tags/pull-wxx-20160322' into staging (2016-03-22 20:27:55 +0000)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20160323
>
> for you to fetch changes up to b7c4ab809a4bfde4ab322b49fbe2e47536da7487:
>
>   default-configs: add mips-softmmu-common.mak (2016-03-23 13:36:56 +0000)
>
> ----------------------------------------------------------------
> MIPS patches 2016-03-23
>
> Changes:
> * add mips-softmmu-common.mak
> * indicate presence of IEEE 754-2008 FPU in MIPS64R6-generic and P5600
>
> ----------------------------------------------------------------


Applied, thanks.

-- PMM

[Qemu-devel] [PULL 0/2] target-mips queue

[Leon Alrae]

Hi,

This pull request contains remaining change for 2.3 which was originally
submitted before soft-freeze.

Thanks,
Leon

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Aurelien Jarno <aurelien@aurel32.net>

The following changes since commit 48412371415a260d00fc7fdcdb400da55f268828:

  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2015-03-11 11:12:35 +0000)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20150311

for you to fetch changes up to 644511117e7ca9f26d633a59c202a297113a796c:

  target-mips: add missing MSACSR and restore fp_status and hflags (2015-03-11 14:13:57 +0000)

----------------------------------------------------------------
MIPS patches 2015-03-11

Changes:
* use VMStateDescription for MIPS CPU

----------------------------------------------------------------
Leon Alrae (2):
      target-mips: replace cpu_save/cpu_load with VMStateDescription
      target-mips: add missing MSACSR and restore fp_status and hflags

 target-mips/cpu-qom.h        |   4 +
 target-mips/cpu.c            |   1 +
 target-mips/cpu.h            |  19 +-
 target-mips/machine.c        | 571 ++++++++++++++++++++-----------------------
 target-mips/msa_helper.c     |  12 +-
 target-mips/translate_init.c |  10 +-
 6 files changed, 288 insertions(+), 329 deletions(-)

Re: [Qemu-devel] [PULL 0/2] target-mips queue

[Peter Maydell]

On 11 March 2015 at 16:15, Leon Alrae <leon.alrae@imgtec.com> wrote:
> Hi,
>
> This pull request contains remaining change for 2.3 which was originally
> submitted before soft-freeze.
>
> Thanks,
> Leon
>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Aurelien Jarno <aurelien@aurel32.net>
>
> The following changes since commit 48412371415a260d00fc7fdcdb400da55f268828:
>
>   Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging (2015-03-11 11:12:35 +0000)
>
> are available in the git repository at:
>
>   git://github.com/lalrae/qemu.git tags/mips-20150311
>
> for you to fetch changes up to 644511117e7ca9f26d633a59c202a297113a796c:
>
>   target-mips: add missing MSACSR and restore fp_status and hflags (2015-03-11 14:13:57 +0000)
>
> ----------------------------------------------------------------
> MIPS patches 2015-03-11
>
> Changes:
> * use VMStateDescription for MIPS CPU
>
> ----------------------------------------------------------------
Applied, thanks.

-- PMM