From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a2lcI-00074i-9a for qemu-devel@nongnu.org; Sat, 28 Nov 2015 14:57:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a2lcH-0000p0-Ex for qemu-devel@nongnu.org; Sat, 28 Nov 2015 14:57:06 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41662) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a2lcH-0000ov-9Y for qemu-devel@nongnu.org; Sat, 28 Nov 2015 14:57:05 -0500 From: Eduardo Habkost Date: Sat, 28 Nov 2015 17:56:50 -0200 Message-Id: <1448740611-3096-3-git-send-email-ehabkost@redhat.com> In-Reply-To: <1448740611-3096-1-git-send-email-ehabkost@redhat.com> References: <1448740611-3096-1-git-send-email-ehabkost@redhat.com> Subject: [Qemu-devel] [for-2.6 PATCH 2/3] target-i386: Use xsave structs for ext_save_area List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , kvm@vger.kernel.org, Huaitong Han This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Signed-off-by: Eduardo Habkost --- target-i386/cpu.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 11e5e39..bc95437 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -458,17 +458,23 @@ typedef struct ExtSaveArea { static const ExtSaveArea ext_save_areas[] = { [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, - .offset = 0x240, .size = 0x100 }, + .offset = offsetof(X86XSaveArea, avx_state), + .size = sizeof(XSaveAVX) }, [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, - .offset = 0x3c0, .size = 0x40 }, + .offset = offsetof(X86XSaveArea, bndreg_state), + .size = sizeof(XSaveBNDREG) }, [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, - .offset = 0x400, .size = 0x40 }, + .offset = offsetof(X86XSaveArea, bndcsr_state), + .size = sizeof(XSaveBNDCSR) }, [5] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, - .offset = 0x440, .size = 0x40 }, + .offset = offsetof(X86XSaveArea, opmask_state), + .size = sizeof(XSaveOpmask) }, [6] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, - .offset = 0x480, .size = 0x200 }, + .offset = offsetof(X86XSaveArea, zmm_hi256_state), + .size = sizeof(XSaveZMM_Hi256) }, [7] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, - .offset = 0x680, .size = 0x400 }, + .offset = offsetof(X86XSaveArea, hi16_zmm_state), + .size = sizeof(XSaveHi16_ZMM) }, }; const char *get_register_name_32(unsigned int reg) -- 2.1.0