From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3K4C-0008VL-FC for qemu-devel@nongnu.org; Mon, 30 Nov 2015 03:44:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a3K49-0002YB-5n for qemu-devel@nongnu.org; Mon, 30 Nov 2015 03:44:12 -0500 From: David Gibson Date: Mon, 30 Nov 2015 19:44:44 +1100 Message-Id: <1448873085-9277-5-git-send-email-david@gibson.dropbear.id.au> In-Reply-To: <1448873085-9277-1-git-send-email-david@gibson.dropbear.id.au> References: <1448873085-9277-1-git-send-email-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 4/5] target-ppc: Move the FPSCR bit update macros to cpu.h List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: lvivier@redhat.com, thuth@redhat.com, qemu-devel@nongnu.org, aik@ozlabs.ru, qemu-stable@nongnu.org, agraf@suse.de, mdroth@linux.vnet.ibm.com, Madhavan Srinivasan , qemu-ppc@nongnu.org, David Gibson From: Madhavan Srinivasan Move the FPSCR bit update macros defined in dfp_helper to cpu.h. This way, fpu_helper functions can also use them Signed-off-by: Madhavan Srinivasan Signed-off-by: David Gibson --- target-ppc/cpu.h | 21 +++++++++++++++++++++ target-ppc/dfp_helper.c | 21 --------------------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 31c6fee..9706000 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -684,6 +684,27 @@ enum { #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ 0x1F) +#define FP_FX (1ull << FPSCR_FX) +#define FP_FEX (1ull << FPSCR_FEX) +#define FP_OX (1ull << FPSCR_OX) +#define FP_OE (1ull << FPSCR_OE) +#define FP_UX (1ull << FPSCR_UX) +#define FP_UE (1ull << FPSCR_UE) +#define FP_XX (1ull << FPSCR_XX) +#define FP_XE (1ull << FPSCR_XE) +#define FP_ZX (1ull << FPSCR_ZX) +#define FP_ZE (1ull << FPSCR_ZE) +#define FP_VX (1ull << FPSCR_VX) +#define FP_VXSNAN (1ull << FPSCR_VXSNAN) +#define FP_VXISI (1ull << FPSCR_VXISI) +#define FP_VXIMZ (1ull << FPSCR_VXIMZ) +#define FP_VXZDZ (1ull << FPSCR_VXZDZ) +#define FP_VXIDI (1ull << FPSCR_VXIDI) +#define FP_VXVC (1ull << FPSCR_VXVC) +#define FP_VXCVI (1ull << FPSCR_VXCVI) +#define FP_VE (1ull << FPSCR_VE) +#define FP_FI (1ull << FPSCR_FI) + /*****************************************************************************/ /* Vector status and control register */ #define VSCR_NJ 16 /* Vector non-java */ diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c index 49820bf..451e434 100644 --- a/target-ppc/dfp_helper.c +++ b/target-ppc/dfp_helper.c @@ -170,27 +170,6 @@ static void dfp_prepare_decimal128(struct PPC_DFP *dfp, uint64_t *a, } } -#define FP_FX (1ull << FPSCR_FX) -#define FP_FEX (1ull << FPSCR_FEX) -#define FP_OX (1ull << FPSCR_OX) -#define FP_OE (1ull << FPSCR_OE) -#define FP_UX (1ull << FPSCR_UX) -#define FP_UE (1ull << FPSCR_UE) -#define FP_XX (1ull << FPSCR_XX) -#define FP_XE (1ull << FPSCR_XE) -#define FP_ZX (1ull << FPSCR_ZX) -#define FP_ZE (1ull << FPSCR_ZE) -#define FP_VX (1ull << FPSCR_VX) -#define FP_VXSNAN (1ull << FPSCR_VXSNAN) -#define FP_VXISI (1ull << FPSCR_VXISI) -#define FP_VXIMZ (1ull << FPSCR_VXIMZ) -#define FP_VXZDZ (1ull << FPSCR_VXZDZ) -#define FP_VXIDI (1ull << FPSCR_VXIDI) -#define FP_VXVC (1ull << FPSCR_VXVC) -#define FP_VXCVI (1ull << FPSCR_VXCVI) -#define FP_VE (1ull << FPSCR_VE) -#define FP_FI (1ull << FPSCR_FI) - static void dfp_set_FPSCR_flag(struct PPC_DFP *dfp, uint64_t flag, uint64_t enabled) { -- 2.5.0