From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a3zyi-0005yk-6d for qemu-devel@nongnu.org; Wed, 02 Dec 2015 00:29:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a3zyf-0001bu-09 for qemu-devel@nongnu.org; Wed, 02 Dec 2015 00:29:20 -0500 Message-ID: <1449034147.2983.25.camel@kernel.crashing.org> From: Benjamin Herrenschmidt Date: Wed, 02 Dec 2015 16:29:07 +1100 In-Reply-To: <565E5656.8060200@ozlabs.ru> References: <1447201710-10229-1-git-send-email-benh@kernel.crashing.org> <1447201710-10229-42-git-send-email-benh@kernel.crashing.org> <564A7584.5060605@ozlabs.ru> <1447720804.3729.17.camel@kernel.crashing.org> <20151201064326.GA4903@voom> <565E5656.8060200@ozlabs.ru> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy , David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Wed, 2015-12-02 at 13:24 +1100, Alexey Kardashevskiy wrote: > > But on the whole I agree with you, since the LPC is part of the P8 > > chip, I think it makes sense to include it even with -nodefaults. >=20 > POWER8 chips all have 8 threads per core but we do not always assume -s= mt=C2=A0 > ...,threads=3D8, how are LPC or PHB different?=20 First, for pseries which is paravirtualized it's a different can of worms completely. For powernv, we *should* represent all 8 threads, we just can't yet due to TCG limitations. > PHB is more interesting - how=C2=A0is the user supposed to add more? That's an open question. Since we model a real P8 chip we can only model the PHBs as they exist on it, which is up to 3 per chip at very specific XSCOM addresses. We could try to model some non-existing P8 chip with more but bad things will happen when the FW try to assign interrupt numbers for example. We simulate a machine that has been primed by HostBoot before OPAL starts. So we rely on what the device-tree tells us of what PHB were enabled but appart from that, we have to stick to the limitations. > And there always will be the default one=C2=A0 > which properties are set in a separate way (via -global, not -device). = I=C2=A0 > found it sometime really annoying to debug the existing pseries which=C2= =A0 > always adds a default PHB (I know, this was to make libvirt happy but t= his=C2=A0 > is not the case here). >=20 > Out of curiosity - if we have 2 chips, will the system work if the seco= nd=C2=A0 > chip does not get any LPC or PHB attached? This is something I need to look into, there's a lot of work needed to properly model "chips" that I haven't done yet, but what is there is sufficient for a lot of usages already. Cheers, Ben.