From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36407) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a4HcA-0004RE-7h for qemu-devel@nongnu.org; Wed, 02 Dec 2015 19:19:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a4Hc7-000228-71 for qemu-devel@nongnu.org; Wed, 02 Dec 2015 19:19:14 -0500 From: Michael Davidsaver Date: Wed, 2 Dec 2015 19:18:43 -0500 Message-Id: <1449101933-24928-17-git-send-email-mdavidsaver@gmail.com> In-Reply-To: <1449101933-24928-1-git-send-email-mdavidsaver@gmail.com> References: <1449101933-24928-1-git-send-email-mdavidsaver@gmail.com> Subject: [Qemu-devel] [PATCH v2 16/26] armv7m: add some mpu debugging prints List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Crosthwaite , qemu-arm@nongnu.org, Michael Davidsaver Provide some more "-d mmu" related to the MPU translation process as an aid in debugging guest MPU configurations. Helpful since our MPU resolution is limited to the ARM7-AR page size. --- target-arm/helper.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 589aa54..da99825 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -7110,7 +7110,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, if (base & rmask) { qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned " - "to DRSR region size, mask = %" PRIx32, + "to DRSR region size, mask = %" PRIx32 "\n", base, rmask); continue; } @@ -7148,9 +7148,9 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, } } if (rsize < TARGET_PAGE_BITS) { - qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region" + qemu_log_mask(LOG_UNIMP, "No support for MPU[%u] (sub)region " "alignment of %" PRIu32 " bits. Minimum is %d\n", - rsize, TARGET_PAGE_BITS); + n, rsize, TARGET_PAGE_BITS); continue; } if (srdis) { @@ -7164,11 +7164,14 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) { /* background fault */ *fsr = 0; + + qemu_log_mask(CPU_LOG_MMU, "Miss MPU\n"); return true; } get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { /* a MPU hit! */ uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3); + qemu_log_mask(CPU_LOG_MMU, "Hit MPU %u AP %08x\n", n, (unsigned)ap); if (is_user) { /* User mode AP bit decoding */ switch (ap) { @@ -7382,9 +7385,15 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, */ if (arm_feature(env, ARM_FEATURE_MPU) && arm_feature(env, ARM_FEATURE_V7)) { + bool ret; *page_size = TARGET_PAGE_SIZE; - return get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); + ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, + phys_ptr, prot, fsr); + qemu_log_mask(CPU_LOG_MMU, "TLB %08x mmu_idx=%u AC %u -> AC %u %s\n", + (unsigned)address, mmu_idx, 1<