From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a4HcA-0004S5-Or for qemu-devel@nongnu.org; Wed, 02 Dec 2015 19:19:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a4Hc9-00023L-HF for qemu-devel@nongnu.org; Wed, 02 Dec 2015 19:19:14 -0500 From: Michael Davidsaver Date: Wed, 2 Dec 2015 19:18:47 -0500 Message-Id: <1449101933-24928-21-git-send-email-mdavidsaver@gmail.com> In-Reply-To: <1449101933-24928-1-git-send-email-mdavidsaver@gmail.com> References: <1449101933-24928-1-git-send-email-mdavidsaver@gmail.com> Subject: [Qemu-devel] [PATCH v2 20/26] armv7m: observable initial register state List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Crosthwaite , qemu-arm@nongnu.org, Michael Davidsaver At least for TI TM4C1294. LR==-1 XPSR==0 PRIMASK, FAULTMASK, and BASEPRI all cleared so exception handlers are unmasked. STKALIGN set. --- target-arm/cpu.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1fa1f96..8b85888 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -175,7 +175,10 @@ static void arm_cpu_reset(CPUState *s) env->v7m.exception_prio = env->v7m.pending_prio = 0x100; - env->daif &= ~PSTATE_I; + env->v7m.ccr = 1<<9; /* STKALIGN */ + + env->daif &= ~(PSTATE_I|PSTATE_F); + env->ZF = 1; rom = rom_ptr(0); if (rom) { /* Address zero is covered by ROM which hasn't yet been @@ -194,6 +197,7 @@ static void arm_cpu_reset(CPUState *s) } env->regs[13] = initial_msp & 0xFFFFFFFC; + env->regs[14] = 0xffffffff; env->regs[15] = initial_pc & ~1; env->thumb = initial_pc & 1; } -- 2.1.4