From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36507) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a4HcC-0004W7-Da for qemu-devel@nongnu.org; Wed, 02 Dec 2015 19:19:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a4HcA-00024Z-Uf for qemu-devel@nongnu.org; Wed, 02 Dec 2015 19:19:16 -0500 From: Michael Davidsaver Date: Wed, 2 Dec 2015 19:18:49 -0500 Message-Id: <1449101933-24928-23-git-send-email-mdavidsaver@gmail.com> In-Reply-To: <1449101933-24928-1-git-send-email-mdavidsaver@gmail.com> References: <1449101933-24928-1-git-send-email-mdavidsaver@gmail.com> Subject: [Qemu-devel] [PATCH v2 22/26] armv7m: priority field mask List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Peter Crosthwaite , qemu-arm@nongnu.org, Michael Davidsaver Many v7m CPUs don't implement all of the 8 bits of the priority fields. Typically, only the top N bits are available. Existing practice implies that writes to unimplemented bits will be ignore, and read as zero. This allows a guest to discover the implemented bits by writing 0xff to (eg. basepri). The value read back will have only the available bits set. --- hw/intc/armv7m_nvic.c | 2 ++ target-arm/cpu-qom.h | 6 ++++++ target-arm/cpu.c | 7 +++++++ target-arm/helper.c | 6 ++++-- 4 files changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2b42d9d..e2410a3 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -149,6 +149,8 @@ void set_prio(NVICState *s, unsigned irq, uint8_t prio) assert(irq > 3); /* only use for configurable prios */ assert(irq < NVIC_MAX_VECTORS); + prio &= s->cpu->v7m_priority_mask; + s->vectors[irq].raw_prio = prio; s->vectors[irq].prio_group = (prio>>(s->prigroup+1)); s->vectors[irq].prio_sub = irq + (prio & submask) * NVIC_MAX_VECTORS; diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 25fb1ce..79cf591 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -108,6 +108,12 @@ typedef struct ARMCPU { /* PMSAv7 MPU number of supported regions */ uint32_t pmsav7_dregion; + /* Some v7-M targets don't impliment the full 8 bits + * of the priority fields. Writes to unimplimented + * bits are treated as zero (guest can discover mask). + */ + uint8_t v7m_priority_mask; + /* PSCI conduit used to invoke PSCI methods * 0 - disabled, 1 - smc, 2 - hvc */ diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 8b85888..27cf482 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -527,6 +527,9 @@ static Property arm_cpu_has_mpu_property = static Property arm_cpu_pmsav7_dregion_property = DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16); +static Property armv7m_priority_mask_property = + DEFINE_PROP_UINT8("priority-mask", ARMCPU, v7m_priority_mask, 0xff); + static void arm_cpu_post_init(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); @@ -565,6 +568,10 @@ static void arm_cpu_post_init(Object *obj) } } + if (IS_M(&cpu->env) && arm_feature(&cpu->env, ARM_FEATURE_V7)) { + qdev_property_add_static(DEVICE(obj), &armv7m_priority_mask_property, + &error_abort); + } } static void arm_cpu_finalizefn(Object *obj) diff --git a/target-arm/helper.c b/target-arm/helper.c index 2661da4..c890b3a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -7569,6 +7569,8 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { + ARMCPU *cpu = arm_env_get_cpu(env); + if (arm_current_el(env) == 0 && reg > 7) { /* only xPSR sub-fields may be written by unprivileged */ return; @@ -7601,10 +7603,10 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) } break; case 17: /* BASEPRI */ - env->v7m.basepri = val & 0xff; + env->v7m.basepri = val & cpu->v7m_priority_mask; break; case 18: /* BASEPRI_MAX */ - val &= 0xff; + val &= cpu->v7m_priority_mask; if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0)) env->v7m.basepri = val; break; -- 2.1.4