From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PATCH 06/11] ppc: cleanup logging
Date: Sat, 12 Dec 2015 11:36:22 +0100 [thread overview]
Message-ID: <1449916587-18312-7-git-send-email-pbonzini@redhat.com> (raw)
In-Reply-To: <1449916587-18312-1-git-send-email-pbonzini@redhat.com>
Avoid "naked" qemu_log, bring documentation for DEBUG #defines
up to date.
Cc: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target-ppc/excp_helper.c | 1 +
target-ppc/mmu-hash32.c | 12 ++----------
target-ppc/mmu-hash64.c | 9 +--------
target-ppc/mmu_helper.c | 15 +++++++--------
target-ppc/timebase_helper.c | 10 ++++++----
target-ppc/translate.c | 22 +++++++++-------------
6 files changed, 26 insertions(+), 43 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 102d789..dbc070c 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -23,6 +23,7 @@
#include "helper_regs.h"
//#define DEBUG_OP
+//#define DEBUG_SOFTWARE_TLB
//#define DEBUG_EXCEPTIONS
#ifdef DEBUG_EXCEPTIONS
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index dfee358..49bf120 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -24,17 +24,10 @@
#include "kvm_ppc.h"
#include "mmu-hash32.h"
-//#define DEBUG_MMU
//#define DEBUG_BAT
-#ifdef DEBUG_MMU
-# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
-#else
-# define LOG_MMU_STATE(cpu) do { } while (0)
-#endif
-
#ifdef DEBUG_BATS
-# define LOG_BATS(...) qemu_log(__VA_ARGS__)
+# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_BATS(...) do { } while (0)
#endif
@@ -281,9 +274,8 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
}
return 1;
default:
- qemu_log("ERROR: instruction should not need "
+ cpu_abort(cs, "ERROR: instruction should not need "
"address translation\n");
- abort();
}
if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
*raddr = eaddr;
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 7df6ede..34e20fa 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -23,17 +23,10 @@
#include "kvm_ppc.h"
#include "mmu-hash64.h"
-//#define DEBUG_MMU
//#define DEBUG_SLB
-#ifdef DEBUG_MMU
-# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
-#else
-# define LOG_MMU_STATE(cpu) do { } while (0)
-#endif
-
#ifdef DEBUG_SLB
-# define LOG_SLB(...) qemu_log(__VA_ARGS__)
+# define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_SLB(...) do { } while (0)
#endif
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 30298d8..5217691 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -28,23 +28,22 @@
//#define DEBUG_BATS
//#define DEBUG_SOFTWARE_TLB
//#define DUMP_PAGE_TABLES
-//#define DEBUG_SOFTWARE_TLB
//#define FLUSH_ALL_TLBS
#ifdef DEBUG_MMU
-# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
+# define LOG_MMU_STATE(cpu) log_cpu_state_mask(CPU_LOG_MMU, (cpu), 0)
#else
# define LOG_MMU_STATE(cpu) do { } while (0)
#endif
#ifdef DEBUG_SOFTWARE_TLB
-# define LOG_SWTLB(...) qemu_log(__VA_ARGS__)
+# define LOG_SWTLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_SWTLB(...) do { } while (0)
#endif
#ifdef DEBUG_BATS
-# define LOG_BATS(...) qemu_log(__VA_ARGS__)
+# define LOG_BATS(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__)
#else
# define LOG_BATS(...) do { } while (0)
#endif
@@ -162,7 +161,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
if (ctx->raddr != (hwaddr)-1ULL) {
/* all matches should have equal RPN, WIMG & PP */
if ((ctx->raddr & mmask) != (pte1 & mmask)) {
- qemu_log("Bad RPN/WIMG/PP\n");
+ qemu_log_mask(CPU_LOG_MMU, "Bad RPN/WIMG/PP\n");
return -3;
}
}
@@ -508,7 +507,7 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
/* Software TLB search */
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
#if defined(DUMP_PAGE_TABLES)
- if (qemu_log_enabled()) {
+ if (qemu_log_mask(CPU_LOG_MMU)) {
hwaddr curaddr;
uint32_t a0, a1, a2, a3;
@@ -575,8 +574,8 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
/* eciwx or ecowx */
return -4;
default:
- qemu_log("ERROR: instruction should not need "
- "address translation\n");
+ qemu_log_mask(CPU_LOG_MMU, "ERROR: instruction should not need "
+ "address translation\n");
return -4;
}
if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
diff --git a/target-ppc/timebase_helper.c b/target-ppc/timebase_helper.c
index 865dcbe..cafa283 100644
--- a/target-ppc/timebase_helper.c
+++ b/target-ppc/timebase_helper.c
@@ -130,13 +130,14 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)
uint32_t val = 0;
if (unlikely(env->dcr_env == NULL)) {
- qemu_log("No DCR environment\n");
+ qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n");
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL |
POWERPC_EXCP_INVAL_INVAL);
} else if (unlikely(ppc_dcr_read(env->dcr_env,
(uint32_t)dcrn, &val) != 0)) {
- qemu_log("DCR read error %d %03x\n", (uint32_t)dcrn, (uint32_t)dcrn);
+ qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n",
+ (uint32_t)dcrn, (uint32_t)dcrn);
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
}
@@ -146,13 +147,14 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)
void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val)
{
if (unlikely(env->dcr_env == NULL)) {
- qemu_log("No DCR environment\n");
+ qemu_log_mask(LOG_GUEST_ERROR, "No DCR environment\n");
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL |
POWERPC_EXCP_INVAL_INVAL);
} else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn,
(uint32_t)val) != 0)) {
- qemu_log("DCR write error %d %03x\n", (uint32_t)dcrn, (uint32_t)dcrn);
+ qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n",
+ (uint32_t)dcrn, (uint32_t)dcrn);
helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
}
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index cdf46dd..4be7eaa 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11530,12 +11530,10 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
}
/* Is opcode *REALLY* valid ? */
if (unlikely(handler->handler == &gen_invalid)) {
- if (qemu_log_enabled()) {
- qemu_log("invalid/unsupported opcode: "
- "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
- opc1(ctx.opcode), opc2(ctx.opcode),
- opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
- }
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: "
+ "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
+ opc1(ctx.opcode), opc2(ctx.opcode),
+ opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
} else {
uint32_t inval;
@@ -11546,13 +11544,11 @@ void gen_intermediate_code(CPUPPCState *env, struct TranslationBlock *tb)
}
if (unlikely((ctx.opcode & inval) != 0)) {
- if (qemu_log_enabled()) {
- qemu_log("invalid bits: %08x for opcode: "
- "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
- ctx.opcode & inval, opc1(ctx.opcode),
- opc2(ctx.opcode), opc3(ctx.opcode),
- ctx.opcode, ctx.nip - 4);
- }
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: "
+ "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
+ ctx.opcode & inval, opc1(ctx.opcode),
+ opc2(ctx.opcode), opc3(ctx.opcode),
+ ctx.opcode, ctx.nip - 4);
gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
break;
}
--
2.5.0
next prev parent reply other threads:[~2015-12-12 10:36 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-12 10:36 [Qemu-devel] [PATCH 00/11] Avoid always-active qemu_log calls Paolo Bonzini
2015-12-12 10:36 ` [Qemu-devel] [PATCH 01/11] qemu-log: introduce qemu_log_separate Paolo Bonzini
2015-12-12 10:36 ` [Qemu-devel] [PATCH 02/11] alpha: convert "naked" qemu_log to tracepoint Paolo Bonzini
2015-12-16 16:59 ` Richard Henderson
2015-12-12 10:36 ` [Qemu-devel] [PATCH 03/11] cris: avoid "naked" qemu_log Paolo Bonzini
2015-12-17 13:32 ` Edgar E. Iglesias
2015-12-12 10:36 ` [Qemu-devel] [PATCH 04/11] microblaze: " Paolo Bonzini
2015-12-17 13:34 ` Edgar E. Iglesias
2015-12-12 10:36 ` [Qemu-devel] [PATCH 05/11] s390x: " Paolo Bonzini
2015-12-12 10:36 ` Paolo Bonzini [this message]
2015-12-14 0:24 ` [Qemu-devel] [PATCH 06/11] ppc: cleanup logging David Gibson
2015-12-12 10:36 ` [Qemu-devel] [PATCH 07/11] tricore: avoid "naked" qemu_log Paolo Bonzini
2015-12-12 19:47 ` Bastian Koppelmann
2015-12-12 20:15 ` Peter Maydell
2015-12-12 10:36 ` [Qemu-devel] [PATCH 08/11] xtensa: " Paolo Bonzini
2015-12-12 10:36 ` [Qemu-devel] [PATCH 09/11] user: introduce "-d page" Paolo Bonzini
2015-12-12 10:36 ` [Qemu-devel] [PATCH 10/11] linux-user: avoid "naked" qemu_log Paolo Bonzini
2015-12-12 15:04 ` Laurent Vivier
2015-12-12 10:39 ` [Qemu-devel] [PATCH 11/11] linux-user: convert DEBUG_SIGNAL logging to tracepoints Paolo Bonzini
2015-12-12 15:08 ` Laurent Vivier
2015-12-15 6:59 ` Thomas Huth
2015-12-15 13:19 ` Paolo Bonzini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1449916587-18312-7-git-send-email-pbonzini@redhat.com \
--to=pbonzini@redhat.com \
--cc=david@gibson.dropbear.id.au \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).