From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohd-0005VC-0n for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a8Ohb-0001se-GX for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:52 -0500 Received: from mail-wm0-x22e.google.com ([2a00:1450:400c:c09::22e]:33947) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohb-0001sE-AP for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:51 -0500 Received: by mail-wm0-x22e.google.com with SMTP id p66so50836624wmp.1 for ; Mon, 14 Dec 2015 00:41:51 -0800 (PST) From: Alvise Rigo Date: Mon, 14 Dec 2015 09:41:27 +0100 Message-Id: <1450082498-27109-4-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> References: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC v6 03/14] Add CPUClass hook to set exclusive range List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Cc: claudio.fontana@huawei.com, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, alex.bennee@linaro.org, rth@twiddle.net Allow each architecture to set the exclusive range at any LoadLink operation through a CPUClass hook. This comes in handy to emulate, for instance, the exclusive monitor implemented in some ARM architectures (more precisely, the Exclusive Reservation Granule). Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- include/qom/cpu.h | 4 ++++ qom/cpu.c | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index c6bb6b6..9e409ce 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -175,6 +175,10 @@ typedef struct CPUClass { void (*cpu_exec_exit)(CPUState *cpu); bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /* Atomic instruction handling */ + void (*cpu_set_excl_protected_range)(CPUState *cpu, hwaddr addr, + hwaddr size); + void (*disas_set_info)(CPUState *cpu, disassemble_info *info); } CPUClass; diff --git a/qom/cpu.c b/qom/cpu.c index fb80d13..a5c25a8 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -203,6 +203,12 @@ static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) return false; } +static void cpu_common_set_excl_range(CPUState *cpu, hwaddr addr, hwaddr size) +{ + cpu->excl_protected_range.begin = addr; + cpu->excl_protected_range.end = addr + size; +} + void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -355,6 +361,7 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->cpu_exec_enter = cpu_common_noop; k->cpu_exec_exit = cpu_common_noop; k->cpu_exec_interrupt = cpu_common_exec_interrupt; + k->cpu_set_excl_protected_range = cpu_common_set_excl_range; dc->realize = cpu_common_realizefn; /* * Reason: CPUs still need special care by board code: wiring up -- 2.6.4