From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohh-0005Zr-SR for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a8Ohg-0001ug-Qs for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:57 -0500 Received: from mail-wm0-x22a.google.com ([2a00:1450:400c:c09::22a]:35186) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8Ohg-0001uc-Lf for qemu-devel@nongnu.org; Mon, 14 Dec 2015 03:41:56 -0500 Received: by mail-wm0-x22a.google.com with SMTP id p66so33021749wmp.0 for ; Mon, 14 Dec 2015 00:41:56 -0800 (PST) From: Alvise Rigo Date: Mon, 14 Dec 2015 09:41:32 +0100 Message-Id: <1450082498-27109-9-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> References: <1450082498-27109-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [RFC v6 08/14] target-arm: Add atomic_clear helper for CLREX insn List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com Cc: claudio.fontana@huawei.com, pbonzini@redhat.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, alex.bennee@linaro.org, rth@twiddle.net Add a simple helper function to emulate the CLREX instruction. Suggested-by: Jani Kokkonen Suggested-by: Claudio Fontana Signed-off-by: Alvise Rigo --- target-arm/helper.h | 2 ++ target-arm/op_helper.c | 6 ++++++ target-arm/translate.c | 1 + 3 files changed, 9 insertions(+) diff --git a/target-arm/helper.h b/target-arm/helper.h index c2a85c7..37cec49 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -532,6 +532,8 @@ DEF_HELPER_2(dc_zva, void, env, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_1(atomic_clear, void, env) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #endif diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 6cd54c8..5a67557 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -50,6 +50,12 @@ static int exception_target_el(CPUARMState *env) return target_el; } +void HELPER(atomic_clear)(CPUARMState *env) +{ + ENV_GET_CPU(env)->excl_protected_range.begin = -1; + ENV_GET_CPU(env)->ll_sc_context = false; +} + uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, uint32_t rn, uint32_t maxindex) { diff --git a/target-arm/translate.c b/target-arm/translate.c index e88d8a3..e0362e0 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7514,6 +7514,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, static void gen_clrex(DisasContext *s) { #ifdef CONFIG_TCG_USE_LDST_EXCL + gen_helper_atomic_clear(cpu_env); #else tcg_gen_movi_i64(cpu_exclusive_addr, -1); #endif -- 2.6.4