From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51024) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9ce0-0000tz-6U for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a9cdu-0006p5-VM for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:12 -0500 Received: from mx1.redhat.com ([209.132.183.28]:39069) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9cdu-0006oy-OB for qemu-devel@nongnu.org; Thu, 17 Dec 2015 12:47:06 -0500 From: Paolo Bonzini Date: Thu, 17 Dec 2015 18:46:09 +0100 Message-Id: <1450374401-31352-14-git-send-email-pbonzini@redhat.com> In-Reply-To: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> References: <1450374401-31352-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 13/45] target-i386/kvm: Hyper-V SynIC MSR's support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Eduardo Habkost , kvm@vger.kernel.org, Marcelo Tosatti , Roman Kagan , Andrey Smetanin , "Denis V. Lunev" , =?UTF-8?q?Andreas=20F=C3=83=C2=A4rber?= , Richard Henderson From: Andrey Smetanin This patch does Hyper-V Synthetic interrupt controller(Hyper-V SynIC) MSR's support and migration. Hyper-V SynIC is enabled by cpu's 'hv-synic' option. This patch does not allow cpu creation if 'hv-synic' option specified but kernel doesn't support Hyper-V SynIC. Changes v3: * removed 'msr_hv_synic_version' migration because it's value always the same * moved SynIC msr's initialization into kvm_arch_init_vcpu Signed-off-by: Andrey Smetanin Reviewed-by: Roman Kagan Signed-off-by: Denis V. Lunev CC: Paolo Bonzini CC: Richard Henderson CC: Eduardo Habkost CC: "Andreas F=C3=83=C2=A4rber" CC: Marcelo Tosatti CC: Roman Kagan CC: Denis V. Lunev CC: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini --- target-i386/cpu-qom.h | 1 + target-i386/cpu.c | 1 + target-i386/cpu.h | 5 ++++ target-i386/kvm.c | 66 +++++++++++++++++++++++++++++++++++++++++++++= +++++- target-i386/machine.c | 37 +++++++++++++++++++++++++++++ 5 files changed, 109 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index e3bfe9d..7ea5b34 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -94,6 +94,7 @@ typedef struct X86CPU { bool hyperv_reset; bool hyperv_vpindex; bool hyperv_runtime; + bool hyperv_synic; bool check_cpuid; bool enforce_cpuid; bool expose_kvm; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 11e5e39..2fdd855 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3146,6 +3146,7 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false), DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false), DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false), + DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false), DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 84edfd0..1168ddf 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -920,6 +920,11 @@ typedef struct CPUX86State { uint64_t msr_hv_tsc; uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS]; uint64_t msr_hv_runtime; + uint64_t msr_hv_synic_control; + uint64_t msr_hv_synic_version; + uint64_t msr_hv_synic_evt_page; + uint64_t msr_hv_synic_msg_page; + uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT]; =20 /* exception/interrupt handling */ int error_code; diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 6dc9846..ca0708a 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -86,6 +86,7 @@ static bool has_msr_hv_crash; static bool has_msr_hv_reset; static bool has_msr_hv_vpindex; static bool has_msr_hv_runtime; +static bool has_msr_hv_synic; static bool has_msr_mtrr; static bool has_msr_xss; =20 @@ -521,7 +522,8 @@ static bool hyperv_enabled(X86CPU *cpu) cpu->hyperv_crash || cpu->hyperv_reset || cpu->hyperv_vpindex || - cpu->hyperv_runtime); + cpu->hyperv_runtime || + cpu->hyperv_synic); } =20 static Error *invtsc_mig_blocker; @@ -610,6 +612,21 @@ int kvm_arch_init_vcpu(CPUState *cs) if (cpu->hyperv_runtime && has_msr_hv_runtime) { c->eax |=3D HV_X64_MSR_VP_RUNTIME_AVAILABLE; } + if (cpu->hyperv_synic) { + int sint; + + if (!has_msr_hv_synic || + kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) { + fprintf(stderr, "Hyper-V SynIC is not supported by kerne= l\n"); + return -ENOSYS; + } + + c->eax |=3D HV_X64_MSR_SYNIC_AVAILABLE; + env->msr_hv_synic_version =3D HV_SYNIC_VERSION_1; + for (sint =3D 0; sint < ARRAY_SIZE(env->msr_hv_synic_sint); = sint++) { + env->msr_hv_synic_sint[sint] =3D HV_SYNIC_SINT_MASKED; + } + } c =3D &cpuid_data.entries[cpuid_i++]; c->function =3D HYPERV_CPUID_ENLIGHTMENT_INFO; if (cpu->hyperv_relaxed_timing) { @@ -956,6 +973,10 @@ static int kvm_get_supported_msrs(KVMState *s) has_msr_hv_runtime =3D true; continue; } + if (kvm_msr_list->indices[i] =3D=3D HV_X64_MSR_SCONTROL)= { + has_msr_hv_synic =3D true; + continue; + } } } =20 @@ -1517,6 +1538,23 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime); } + if (cpu->hyperv_synic) { + int j; + + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SCONTROL, + env->msr_hv_synic_control); + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SVERSION, + env->msr_hv_synic_version); + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIEFP, + env->msr_hv_synic_evt_page); + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SIMP, + env->msr_hv_synic_msg_page); + + for (j =3D 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) { + kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_SINT0 + j, + env->msr_hv_synic_sint[j]); + } + } if (has_msr_mtrr) { kvm_msr_entry_set(&msrs[n++], MSR_MTRRdefType, env->mtrr_def= type); kvm_msr_entry_set(&msrs[n++], @@ -1885,6 +1923,17 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_hv_runtime) { msrs[n++].index =3D HV_X64_MSR_VP_RUNTIME; } + if (cpu->hyperv_synic) { + uint32_t msr; + + msrs[n++].index =3D HV_X64_MSR_SCONTROL; + msrs[n++].index =3D HV_X64_MSR_SVERSION; + msrs[n++].index =3D HV_X64_MSR_SIEFP; + msrs[n++].index =3D HV_X64_MSR_SIMP; + for (msr =3D HV_X64_MSR_SINT0; msr <=3D HV_X64_MSR_SINT15; msr++= ) { + msrs[n++].index =3D msr; + } + } if (has_msr_mtrr) { msrs[n++].index =3D MSR_MTRRdefType; msrs[n++].index =3D MSR_MTRRfix64K_00000; @@ -2041,6 +2090,21 @@ static int kvm_get_msrs(X86CPU *cpu) case HV_X64_MSR_VP_RUNTIME: env->msr_hv_runtime =3D msrs[i].data; break; + case HV_X64_MSR_SCONTROL: + env->msr_hv_synic_control =3D msrs[i].data; + break; + case HV_X64_MSR_SVERSION: + env->msr_hv_synic_version =3D msrs[i].data; + break; + case HV_X64_MSR_SIEFP: + env->msr_hv_synic_evt_page =3D msrs[i].data; + break; + case HV_X64_MSR_SIMP: + env->msr_hv_synic_msg_page =3D msrs[i].data; + break; + case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: + env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] =3D msrs[i]= .data; + break; case MSR_MTRRdefType: env->mtrr_deftype =3D msrs[i].data; break; diff --git a/target-i386/machine.c b/target-i386/machine.c index a18e16e..d41e286 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -710,6 +710,42 @@ static const VMStateDescription vmstate_msr_hyperv_r= untime =3D { } }; =20 +static bool hyperv_synic_enable_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + int i; + + if (env->msr_hv_synic_control !=3D 0 || + env->msr_hv_synic_evt_page !=3D 0 || + env->msr_hv_synic_msg_page !=3D 0) { + return true; + } + + for (i =3D 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { + if (env->msr_hv_synic_sint[i] !=3D 0) { + return true; + } + } + + return false; +} + +static const VMStateDescription vmstate_msr_hyperv_synic =3D { + .name =3D "cpu/msr_hyperv_synic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D hyperv_synic_enable_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU), + VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU), + VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU), + VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU, + HV_SYNIC_SINT_COUNT), + VMSTATE_END_OF_LIST() + } +}; + static bool avx512_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -893,6 +929,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_hyperv_time, &vmstate_msr_hyperv_crash, &vmstate_msr_hyperv_runtime, + &vmstate_msr_hyperv_synic, &vmstate_avx512, &vmstate_xss, NULL --=20 2.5.0