From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53181) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9e60-0004Rz-3c for qemu-devel@nongnu.org; Thu, 17 Dec 2015 14:20:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a9e5w-0006cy-18 for qemu-devel@nongnu.org; Thu, 17 Dec 2015 14:20:12 -0500 Received: from mail-qk0-x236.google.com ([2607:f8b0:400d:c09::236]:36333) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a9e5v-0006cb-RZ for qemu-devel@nongnu.org; Thu, 17 Dec 2015 14:20:07 -0500 Received: by mail-qk0-x236.google.com with SMTP id t125so102703400qkh.3 for ; Thu, 17 Dec 2015 11:20:07 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Thu, 17 Dec 2015 11:19:24 -0800 Message-Id: <1450379966-28198-9-git-send-email-rth@twiddle.net> In-Reply-To: <1450379966-28198-1-git-send-email-rth@twiddle.net> References: <1450379966-28198-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 08/10] target-i386: Rewrite leave List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, aurelien@aurel32.net, peter.maydell@linaro.org Unify the code across stack pointer widths. Fix the note about not updating ESP before the potential exception. Signed-off-by: Richard Henderson --- target-i386/translate.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index b6749ff..2be4ba8 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2362,6 +2362,20 @@ static void gen_enter(DisasContext *s, int esp_addend, int level) gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]); } +static void gen_leave(DisasContext *s) +{ + TCGMemOp d_ot = mo_pushpop(s, s->dflag); + TCGMemOp a_ot = mo_stacksize(s); + + gen_lea_v_seg(s, a_ot, cpu_regs[R_EBP], R_SS, -1); + gen_op_ld_v(s, d_ot, cpu_T[0], cpu_A0); + + tcg_gen_addi_tl(cpu_T[1], cpu_regs[R_EBP], 1 << d_ot); + + gen_op_mov_reg_v(d_ot, R_EBP, cpu_T[0]); + gen_op_mov_reg_v(a_ot, R_ESP, cpu_T[1]); +} + static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) { gen_update_cc_op(s); @@ -5117,20 +5131,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } break; case 0xc9: /* leave */ - /* XXX: exception not precise (ESP is updated before potential exception) */ - if (CODE64(s)) { - gen_op_mov_v_reg(MO_64, cpu_T[0], R_EBP); - gen_op_mov_reg_v(MO_64, R_ESP, cpu_T[0]); - } else if (s->ss32) { - gen_op_mov_v_reg(MO_32, cpu_T[0], R_EBP); - gen_op_mov_reg_v(MO_32, R_ESP, cpu_T[0]); - } else { - gen_op_mov_v_reg(MO_16, cpu_T[0], R_EBP); - gen_op_mov_reg_v(MO_16, R_ESP, cpu_T[0]); - } - ot = gen_pop_T0(s); - gen_op_mov_reg_v(ot, R_EBP, cpu_T[0]); - gen_pop_update(s, ot); + gen_leave(s); break; case 0x06: /* push es */ case 0x0e: /* push cs */ -- 2.5.0