From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: mark.cave-ayland@ilande.co.uk, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH 25/25] target-sparc: Elide duplicate updates to fprs
Date: Thu, 17 Dec 2015 12:57:25 -0800 [thread overview]
Message-ID: <1450385845-3085-1-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1450385695-1940-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/translate.c | 45 +++++++++++++++++++++++++++------------------
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 4b6b12f..0df45af 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -84,6 +84,7 @@ typedef struct DisasContext {
int n_t32;
int n_ttl;
#ifdef TARGET_SPARC64
+ int fprs_dirty;
int asi;
#endif
} DisasContext;
@@ -141,10 +142,16 @@ static inline TCGv get_temp_tl(DisasContext *dc)
return t;
}
-static inline void gen_update_fprs_dirty(int rd)
+static inline void gen_update_fprs_dirty(DisasContext *dc, int rd)
{
#if defined(TARGET_SPARC64)
- tcg_gen_ori_i32(cpu_fprs, cpu_fprs, (rd < 32) ? 1 : 2);
+ int bit = (rd < 32) ? 1 : 2;
+ /* If we know we've already set this bit within the TB,
+ we can avoid setting it again. */
+ if (!(dc->fprs_dirty & bit)) {
+ dc->fprs_dirty |= bit;
+ tcg_gen_ori_i32(cpu_fprs, cpu_fprs, bit);
+ }
#endif
}
@@ -186,7 +193,7 @@ static void gen_store_fpr_F(DisasContext *dc, unsigned int dst, TCGv_i32 v)
tcg_gen_deposit_i64(cpu_fpr[dst / 2], cpu_fpr[dst / 2], t,
(dst & 1 ? 0 : 32), 32);
#endif
- gen_update_fprs_dirty(dst);
+ gen_update_fprs_dirty(dc, dst);
}
static TCGv_i32 gen_dest_fpr_F(DisasContext *dc)
@@ -204,7 +211,7 @@ static void gen_store_fpr_D(DisasContext *dc, unsigned int dst, TCGv_i64 v)
{
dst = DFPREG(dst);
tcg_gen_mov_i64(cpu_fpr[dst / 2], v);
- gen_update_fprs_dirty(dst);
+ gen_update_fprs_dirty(dc, dst);
}
static TCGv_i64 gen_dest_fpr_D(DisasContext *dc, unsigned int dst)
@@ -237,14 +244,14 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
}
#ifdef TARGET_SPARC64
-static void gen_move_Q(unsigned int rd, unsigned int rs)
+static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
{
rd = QFPREG(rd);
rs = QFPREG(rs);
tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
- gen_update_fprs_dirty(rd);
+ gen_update_fprs_dirty(dc, rd);
}
#endif
@@ -1825,7 +1832,7 @@ static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
}
#ifdef TARGET_SPARC64
@@ -1837,7 +1844,7 @@ static inline void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
gen(cpu_env);
gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
}
#endif
@@ -1851,7 +1858,7 @@ static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
}
static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
@@ -1882,7 +1889,7 @@ static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
gen_helper_check_ieee_exceptions(cpu_fsr, cpu_env);
gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
}
#ifdef TARGET_SPARC64
@@ -1969,7 +1976,7 @@ static inline void gen_ne_fop_QF(DisasContext *dc, int rd, int rs,
gen(cpu_env, src);
gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
}
static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
@@ -1982,7 +1989,7 @@ static inline void gen_ne_fop_QD(DisasContext *dc, int rd, int rs,
gen(cpu_env, src);
gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
}
/* asi moves */
@@ -2770,7 +2777,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
tcg_gen_movcond_i64(cmp->cond, cpu_fpr[qd / 2 + 1], cmp->c1, cmp->c2,
cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]);
- gen_update_fprs_dirty(qd);
+ gen_update_fprs_dirty(dc, qd);
}
#ifndef CONFIG_USER_ONLY
@@ -3556,7 +3563,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
break;
case 0x3: /* V9 fmovq */
CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_move_Q(rd, rs2);
+ gen_move_Q(dc, rd, rs2);
break;
case 0x6: /* V9 fnegd */
gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
@@ -4106,6 +4113,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x6: /* V9 wrfprs */
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0);
+ dc->fprs_dirty = 0;
save_state(dc);
gen_op_next_insn();
tcg_gen_exit_tb(0);
@@ -5207,14 +5215,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto jmp_insn;
}
gen_ldf_asi(dc, cpu_addr, insn, 4, rd);
- gen_update_fprs_dirty(rd);
+ gen_update_fprs_dirty(dc, rd);
goto skip_move;
case 0x33: /* V9 lddfa */
if (gen_trap_ifnofpu(dc)) {
goto jmp_insn;
}
gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
- gen_update_fprs_dirty(DFPREG(rd));
+ gen_update_fprs_dirty(dc, DFPREG(rd));
goto skip_move;
case 0x3d: /* V9 prefetcha, no effect */
goto skip_move;
@@ -5224,7 +5232,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
goto jmp_insn;
}
gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
goto skip_move;
#endif
default:
@@ -5276,7 +5284,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
gen_helper_ldqf(cpu_env, cpu_addr, r_const);
tcg_temp_free_i32(r_const);
gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(QFPREG(rd));
+ gen_update_fprs_dirty(dc, QFPREG(rd));
}
break;
case 0x23: /* lddf, load double fpreg */
@@ -5544,6 +5552,7 @@ void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
dc->address_mask_32bit = tb_am_enabled(tb->flags);
dc->singlestep = (cs->singlestep_enabled || singlestep);
#ifdef TARGET_SPARC64
+ dc->fprs_dirty = 0;
dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
#endif
--
2.5.0
next prev parent reply other threads:[~2015-12-17 20:57 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-17 20:54 [Qemu-devel] [PATCH 00/25] target-sparc improvements Richard Henderson
2015-12-17 20:54 ` [Qemu-devel] [PATCH 01/25] target-sparc: Mark more flags for helpers Richard Henderson
2015-12-17 20:54 ` [Qemu-devel] [PATCH 02/25] target-sparc: Remove softint as a TCG global Richard Henderson
2015-12-17 20:54 ` [Qemu-devel] [PATCH 03/25] target-sparc: Store mmu index in TB flags Richard Henderson
2015-12-17 20:54 ` [Qemu-devel] [PATCH 04/25] target-sparc: Create gen_exception Richard Henderson
2015-12-17 20:56 ` [Qemu-devel] [PATCH 10/25] target-sparc: Add UA2011 defines to asi.h Richard Henderson
2016-01-12 13:17 ` Artyom Tarasenko
2015-12-17 20:57 ` [Qemu-devel] [PATCH 12/25] target-sparc: Add MMU_REAL_IDX Richard Henderson
2016-01-11 11:15 ` Artyom Tarasenko
2016-01-11 12:01 ` Artyom Tarasenko
2015-12-17 20:57 ` [Qemu-devel] [PATCH 14/25] target-sparc: Use QT0 to return results from ldda Richard Henderson
2015-12-17 20:57 ` [Qemu-devel] [PATCH 15/25] target-sparc: Introduce gen_check_align Richard Henderson
2015-12-17 20:57 ` [Qemu-devel] [PATCH 17/25] target-sparc: Fix obvious error in ASI_M_BFILL Richard Henderson
2015-12-17 20:57 ` [Qemu-devel] [PATCH 19/25] target-sparc: Directly implement easy ldf/stf asis Richard Henderson
2015-12-17 20:57 ` [Qemu-devel] [PATCH 20/25] target-sparc: Directly implement block and short " Richard Henderson
2015-12-17 20:57 ` [Qemu-devel] [PATCH 21/25] target-sparc: Remove helper_ldf_asi, helper_stf_asi Richard Henderson
2015-12-17 20:57 ` [Qemu-devel] [PATCH 23/25] target-sparc: Use cpu_fsr in stfsr Richard Henderson
2015-12-17 20:57 ` [Qemu-devel] [PATCH 24/25] target-sparc: Use cpu_loop_exit_restore from helper_check_ieee_exceptions Richard Henderson
2015-12-17 20:57 ` Richard Henderson [this message]
2015-12-17 23:11 ` [Qemu-devel] [PATCH 06/25] target-sparc: Store %asi in TB flags Richard Henderson
2015-12-17 23:11 ` [Qemu-devel] [PATCH 08/25] target-sparc: Pass TCGMemOp to gen_ld/st_asi Richard Henderson
2015-12-17 23:13 ` [Qemu-devel] [PATCH 00/25] target-sparc improvements Richard Henderson
2015-12-29 18:59 ` Mark Cave-Ayland
2016-01-08 15:08 ` Richard Henderson
2016-01-15 20:44 ` Artyom Tarasenko
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