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From: James Hogan <james.hogan@imgtec.com>
To: qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>
Cc: James Hogan <james.hogan@imgtec.com>,
	Leon Alrae <leon.alrae@imgtec.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	kvm@vger.kernel.org
Subject: [Qemu-devel] [PATCH v4 2/7] mips/kvm: Implement PRid CP0 register
Date: Fri, 18 Dec 2015 10:45:59 +0000	[thread overview]
Message-ID: <1450435564-30720-3-git-send-email-james.hogan@imgtec.com> (raw)
In-Reply-To: <1450435564-30720-1-git-send-email-james.hogan@imgtec.com>

Implement saving and restoring to KVM state of the Processor ID (PRid)
CP0 register. This allows QEMU to control the PRid exposed to the guest
instead of using the default set by KVM.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
---
 target-mips/kvm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/target-mips/kvm.c b/target-mips/kvm.c
index 5cd65ad201ca..41abc8709d96 100644
--- a/target-mips/kvm.c
+++ b/target-mips/kvm.c
@@ -228,6 +228,7 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level)
 #define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
 #define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
 #define KVM_REG_MIPS_CP0_EPC            MIPS_CP0_64(14, 0)
+#define KVM_REG_MIPS_CP0_PRID           MIPS_CP0_32(15, 0)
 #define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 
 static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id,
@@ -520,6 +521,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level)
         DPRINTF("%s: Failed to put CP0_EPC (%d)\n", __func__, err);
         ret = err;
     }
+    err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
+    if (err < 0) {
+        DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err);
+        ret = err;
+    }
     err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
                                  &env->CP0_ErrorEPC);
     if (err < 0) {
@@ -606,6 +612,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs)
         DPRINTF("%s: Failed to get CP0_EPC (%d)\n", __func__, err);
         ret = err;
     }
+    err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PRID, &env->CP0_PRid);
+    if (err < 0) {
+        DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err);
+        ret = err;
+    }
     err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC,
                                  &env->CP0_ErrorEPC);
     if (err < 0) {
-- 
2.4.10

  parent reply	other threads:[~2015-12-18 10:46 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-12-18 10:45 [Qemu-devel] [PATCH v4 0/7] mips/kvm: Support FPU & SIMD (MSA) in MIPS KVM guests James Hogan
2015-12-18 10:45 ` [Qemu-devel] [PATCH v4 1/7] mips/kvm: Remove a couple of noisy DPRINTFs James Hogan
2015-12-18 10:45 ` James Hogan [this message]
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 3/7] mips/kvm: Implement Config CP0 registers James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 4/7] mips/kvm: Support unsigned KVM registers James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 5/7] mips/kvm: Support signed 64-bit " James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 6/7] mips/kvm: Support FPU in MIPS KVM guests James Hogan
2015-12-18 10:46 ` [Qemu-devel] [PATCH v4 7/7] mips/kvm: Support MSA " James Hogan
2016-02-02  9:58   ` Leon Alrae
2016-02-02 12:39     ` James Hogan
2016-02-02 13:56       ` Leon Alrae

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