From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58141) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aDpHx-0003Os-HP for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aDpHt-0001ge-Rg for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:49 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Tue, 29 Dec 2015 09:04:51 +0100 Message-Id: <1451376295-28834-15-git-send-email-hpoussin@reactos.org> In-Reply-To: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> References: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 13/17] fdc: use IsaDma interface instead of global DMA_* functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Kevin Wolf , "open list:Floppy" , "Michael S. Tsirkin" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Paolo Bonzini , John Snow Signed-off-by: Herv=C3=A9 Poussineau --- hw/block/fdc.c | 63 ++++++++++++++++++++++++++++++++++++++++++----------= ------ 1 file changed, 46 insertions(+), 17 deletions(-) diff --git a/hw/block/fdc.c b/hw/block/fdc.c index 14891c1..3c3d046 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -534,6 +534,7 @@ struct FDCtrl { QEMUTimer *result_timer; int dma_chann; uint8_t phase; + IsaDma *dma; /* Controller's identification */ uint8_t version; /* HW */ @@ -1313,7 +1314,8 @@ static void fdctrl_stop_transfer(FDCtrl *fdctrl, ui= nt8_t status0, fdctrl->fifo[6] =3D FD_SECTOR_SC; fdctrl->data_dir =3D FD_DIR_READ; if (!(fdctrl->msr & FD_MSR_NONDMA)) { - DMA_release_DREQ(fdctrl->dma_chann); + IsaDmaClass *k =3D ISADMA_GET_CLASS(fdctrl->dma); + k->release_DREQ(fdctrl->dma, fdctrl->dma_chann); } fdctrl->msr |=3D FD_MSR_RQM | FD_MSR_DIO; fdctrl->msr &=3D ~FD_MSR_NONDMA; @@ -1399,27 +1401,43 @@ static void fdctrl_start_transfer(FDCtrl *fdctrl,= int direction) } fdctrl->eot =3D fdctrl->fifo[6]; if (fdctrl->dor & FD_DOR_DMAEN) { - int dma_mode; + IsaDmaTransferMode dma_mode; + IsaDmaClass *k =3D ISADMA_GET_CLASS(fdctrl->dma); + bool dma_mode_ok; /* DMA transfer are enabled. Check if DMA channel is well progra= mmed */ - dma_mode =3D DMA_get_channel_mode(fdctrl->dma_chann); - dma_mode =3D (dma_mode >> 2) & 3; + dma_mode =3D k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann= ); FLOPPY_DPRINTF("dma_mode=3D%d direction=3D%d (%d - %d)\n", dma_mode, direction, (128 << fdctrl->fifo[5]) * (cur_drv->last_sect - ks + 1), fdctrl->data_len); - if (((direction =3D=3D FD_DIR_SCANE || direction =3D=3D FD_DIR_S= CANL || - direction =3D=3D FD_DIR_SCANH) && dma_mode =3D=3D 0) || - (direction =3D=3D FD_DIR_WRITE && dma_mode =3D=3D 2) || - (direction =3D=3D FD_DIR_READ && dma_mode =3D=3D 1) || - (direction =3D=3D FD_DIR_VERIFY)) { + switch (direction) { + case FD_DIR_SCANE: + case FD_DIR_SCANL: + case FD_DIR_SCANH: + dma_mode_ok =3D (dma_mode =3D=3D ISADMA_TRANSFER_VERIFY); + break; + case FD_DIR_WRITE: + dma_mode_ok =3D (dma_mode =3D=3D ISADMA_TRANSFER_WRITE); + break; + case FD_DIR_READ: + dma_mode_ok =3D (dma_mode =3D=3D ISADMA_TRANSFER_READ); + break; + case FD_DIR_VERIFY: + dma_mode_ok =3D true; + break; + default: + dma_mode_ok =3D false; + break; + } + if (dma_mode_ok) { /* No access is allowed until DMA transfer has completed */ fdctrl->msr &=3D ~FD_MSR_RQM; if (direction !=3D FD_DIR_VERIFY) { /* Now, we just have to wait for the DMA controller to * recall us... */ - DMA_hold_DREQ(fdctrl->dma_chann); - DMA_schedule(); + k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann); + k->schedule(fdctrl->dma); } else { /* Start transfer */ fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, @@ -1458,12 +1476,14 @@ static int fdctrl_transfer_handler (void *opaque,= int nchan, FDrive *cur_drv; int len, start_pos, rel_pos; uint8_t status0 =3D 0x00, status1 =3D 0x00, status2 =3D 0x00; + IsaDmaClass *k; =20 fdctrl =3D opaque; if (fdctrl->msr & FD_MSR_RQM) { FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); return 0; } + k =3D ISADMA_GET_CLASS(fdctrl->dma); cur_drv =3D get_cur_drv(fdctrl); if (fdctrl->data_dir =3D=3D FD_DIR_SCANE || fdctrl->data_dir =3D=3D = FD_DIR_SCANL || fdctrl->data_dir =3D=3D FD_DIR_SCANH) @@ -1502,8 +1522,8 @@ static int fdctrl_transfer_handler (void *opaque, i= nt nchan, switch (fdctrl->data_dir) { case FD_DIR_READ: /* READ commands */ - DMA_write_memory (nchan, fdctrl->fifo + rel_pos, - fdctrl->data_pos, len); + k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, + fdctrl->data_pos, len); break; case FD_DIR_WRITE: /* WRITE commands */ @@ -1517,8 +1537,8 @@ static int fdctrl_transfer_handler (void *opaque, i= nt nchan, goto transfer_error; } =20 - DMA_read_memory (nchan, fdctrl->fifo + rel_pos, - fdctrl->data_pos, len); + k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos, + fdctrl->data_pos, len); if (blk_write(cur_drv->blk, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) { FLOPPY_DPRINTF("error writing sector %d\n", @@ -1535,7 +1555,8 @@ static int fdctrl_transfer_handler (void *opaque, i= nt nchan, { uint8_t tmpbuf[FD_SECTOR_LEN]; int ret; - DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); + k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_= pos, + len); ret =3D memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); if (ret =3D=3D 0) { status2 =3D FD_SR2_SEH; @@ -2325,7 +2346,11 @@ static void fdctrl_realize_common(FDCtrl *fdctrl, = Error **errp) fdctrl->num_floppies =3D MAX_FD; =20 if (fdctrl->dma_chann !=3D -1) { - DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler= , fdctrl); + IsaDmaClass *k; + assert(fdctrl->dma); + k =3D ISADMA_GET_CLASS(fdctrl->dma); + k->register_channel(fdctrl->dma, fdctrl->dma_chann, + &fdctrl_transfer_handler, fdctrl); } fdctrl_connect_drives(fdctrl, errp); } @@ -2348,6 +2373,10 @@ static void isabus_fdc_realize(DeviceState *dev, E= rror **errp) =20 isa_init_irq(isadev, &fdctrl->irq, isa->irq); fdctrl->dma_chann =3D isa->dma; + if (fdctrl->dma_chann !=3D -1) { + fdctrl->dma =3D isa_get_dma(isa_bus_from_device(isadev), isa->dm= a); + assert(fdctrl->dma); + } =20 qdev_set_legacy_instance_id(dev, isa->iobase, 2); fdctrl_realize_common(fdctrl, &err); --=20 2.1.4