From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57955) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aDpHn-0003B8-MV for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aDpHj-0001bb-LO for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:39 -0500 Received: from smtp5-g21.free.fr ([212.27.42.5]:17814) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aDpHj-0001ax-Co for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:35 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Tue, 29 Dec 2015 09:04:40 +0100 Message-Id: <1451376295-28834-4-git-send-email-hpoussin@reactos.org> In-Reply-To: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> References: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 03/17] i8257: rename struct dma_cont to I8257State List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , "Michael S. Tsirkin" Signed-off-by: Herv=C3=A9 Poussineau --- hw/dma/i8257.c | 43 +++++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index 4d0b49d..f4fcf39 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -52,7 +52,7 @@ struct dma_regs { #define ADDR 0 #define COUNT 1 =20 -static struct dma_cont { +typedef struct I8257State { uint8_t status; uint8_t command; uint8_t mask; @@ -61,7 +61,9 @@ static struct dma_cont { struct dma_regs regs[4]; MemoryRegion channel_io; MemoryRegion cont_io; -} dma_controllers[2]; +} I8257State; + +static I8257State dma_controllers[2]; =20 enum { CMD_MEMORY_TO_MEMORY =3D 0x01, @@ -84,7 +86,7 @@ static int channels[8] =3D {-1, 2, 3, 1, -1, -1, -1, 0}= ; =20 static void write_page (void *opaque, uint32_t nport, uint32_t data) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int ichan; =20 ichan =3D channels[nport & 7]; @@ -97,7 +99,7 @@ static void write_page (void *opaque, uint32_t nport, u= int32_t data) =20 static void write_pageh (void *opaque, uint32_t nport, uint32_t data) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int ichan; =20 ichan =3D channels[nport & 7]; @@ -110,7 +112,7 @@ static void write_pageh (void *opaque, uint32_t nport= , uint32_t data) =20 static uint32_t read_page (void *opaque, uint32_t nport) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int ichan; =20 ichan =3D channels[nport & 7]; @@ -123,7 +125,7 @@ static uint32_t read_page (void *opaque, uint32_t npo= rt) =20 static uint32_t read_pageh (void *opaque, uint32_t nport) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int ichan; =20 ichan =3D channels[nport & 7]; @@ -134,7 +136,7 @@ static uint32_t read_pageh (void *opaque, uint32_t np= ort) return d->regs[ichan].pageh; } =20 -static inline void init_chan (struct dma_cont *d, int ichan) +static inline void init_chan(I8257State *d, int ichan) { struct dma_regs *r; =20 @@ -143,7 +145,7 @@ static inline void init_chan (struct dma_cont *d, int= ichan) r->now[COUNT] =3D 0; } =20 -static inline int getff (struct dma_cont *d) +static inline int getff(I8257State *d) { int ff; =20 @@ -154,7 +156,7 @@ static inline int getff (struct dma_cont *d) =20 static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int ichan, nreg, iport, ff, val, dir; struct dma_regs *r; =20 @@ -177,7 +179,7 @@ static uint64_t read_chan(void *opaque, hwaddr nport,= unsigned size) static void write_chan(void *opaque, hwaddr nport, uint64_t data, unsigned size) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int iport, ichan, nreg; struct dma_regs *r; =20 @@ -196,7 +198,7 @@ static void write_chan(void *opaque, hwaddr nport, ui= nt64_t data, static void write_cont(void *opaque, hwaddr nport, uint64_t data, unsigned size) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int iport, ichan =3D 0; =20 iport =3D (nport >> d->dshift) & 0x0f; @@ -284,7 +286,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, =20 static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; int iport, val; =20 iport =3D (nport >> d->dshift) & 0x0f; @@ -361,7 +363,7 @@ static bool dma_bh_scheduled; =20 static void DMA_run (void) { - struct dma_cont *d; + I8257State *d; int icont, ichan; int rearm =3D 0; static int running =3D 0; @@ -473,7 +475,7 @@ void DMA_schedule(void) =20 static void dma_reset(void *opaque) { - struct dma_cont *d =3D opaque; + I8257State *d =3D opaque; write_cont(d, (0x05 << d->dshift), 0, 1); } =20 @@ -519,7 +521,7 @@ static const MemoryRegionOps cont_io_ops =3D { }; =20 /* dshift =3D 0: 8 bit DMA, 1 =3D 16 bit DMA */ -static void dma_init2(struct dma_cont *d, int base, int dshift, +static void dma_init2(I8257State *d, int base, int dshift, int page_base, int pageh_base) { int i; @@ -579,11 +581,12 @@ static const VMStateDescription vmstate_dma =3D { .minimum_version_id =3D 1, .post_load =3D dma_post_load, .fields =3D (VMStateField[]) { - VMSTATE_UINT8(command, struct dma_cont), - VMSTATE_UINT8(mask, struct dma_cont), - VMSTATE_UINT8(flip_flop, struct dma_cont), - VMSTATE_INT32(dshift, struct dma_cont), - VMSTATE_STRUCT_ARRAY(regs, struct dma_cont, 4, 1, vmstate_dma_re= gs, struct dma_regs), + VMSTATE_UINT8(command, I8257State), + VMSTATE_UINT8(mask, I8257State), + VMSTATE_UINT8(flip_flop, I8257State), + VMSTATE_INT32(dshift, I8257State), + VMSTATE_STRUCT_ARRAY(regs, I8257State, 4, 1, vmstate_dma_regs, + struct dma_regs), VMSTATE_END_OF_LIST() } }; --=20 2.1.4