From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57948) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aDpHn-0003B6-LL for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aDpHj-0001bW-Kp for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:39 -0500 Received: from smtp5-g21.free.fr ([2a01:e0c:1:1599::14]:55483) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aDpHj-0001b5-Cr for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:35 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Tue, 29 Dec 2015 09:04:41 +0100 Message-Id: <1451376295-28834-5-git-send-email-hpoussin@reactos.org> In-Reply-To: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> References: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 04/17] i8257: rename functions to start with i8257_ prefix List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , "Michael S. Tsirkin" Signed-off-by: Herv=C3=A9 Poussineau --- hw/dma/i8257.c | 91 +++++++++++++++++++++++++++++-----------------------= ------ 1 file changed, 46 insertions(+), 45 deletions(-) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index f4fcf39..aba4295 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -80,11 +80,11 @@ enum { =20 }; =20 -static void DMA_run (void); +static void i8257_dma_run(void); =20 static int channels[8] =3D {-1, 2, 3, 1, -1, -1, -1, 0}; =20 -static void write_page (void *opaque, uint32_t nport, uint32_t data) +static void i8257_write_page(void *opaque, uint32_t nport, uint32_t data= ) { I8257State *d =3D opaque; int ichan; @@ -97,7 +97,7 @@ static void write_page (void *opaque, uint32_t nport, u= int32_t data) d->regs[ichan].page =3D data; } =20 -static void write_pageh (void *opaque, uint32_t nport, uint32_t data) +static void i8257_write_pageh(void *opaque, uint32_t nport, uint32_t dat= a) { I8257State *d =3D opaque; int ichan; @@ -110,7 +110,7 @@ static void write_pageh (void *opaque, uint32_t nport= , uint32_t data) d->regs[ichan].pageh =3D data; } =20 -static uint32_t read_page (void *opaque, uint32_t nport) +static uint32_t i8257_read_page(void *opaque, uint32_t nport) { I8257State *d =3D opaque; int ichan; @@ -123,7 +123,7 @@ static uint32_t read_page (void *opaque, uint32_t npo= rt) return d->regs[ichan].page; } =20 -static uint32_t read_pageh (void *opaque, uint32_t nport) +static uint32_t i8257_read_pageh(void *opaque, uint32_t nport) { I8257State *d =3D opaque; int ichan; @@ -136,7 +136,7 @@ static uint32_t read_pageh (void *opaque, uint32_t np= ort) return d->regs[ichan].pageh; } =20 -static inline void init_chan(I8257State *d, int ichan) +static inline void i8257_init_chan(I8257State *d, int ichan) { struct dma_regs *r; =20 @@ -145,7 +145,7 @@ static inline void init_chan(I8257State *d, int ichan= ) r->now[COUNT] =3D 0; } =20 -static inline int getff(I8257State *d) +static inline int i8257_getff(I8257State *d) { int ff; =20 @@ -154,7 +154,7 @@ static inline int getff(I8257State *d) return ff; } =20 -static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) +static uint64_t i8257_read_chan(void *opaque, hwaddr nport, unsigned siz= e) { I8257State *d =3D opaque; int ichan, nreg, iport, ff, val, dir; @@ -166,7 +166,7 @@ static uint64_t read_chan(void *opaque, hwaddr nport,= unsigned size) r =3D d->regs + ichan; =20 dir =3D ((r->mode >> 5) & 1) ? -1 : 1; - ff =3D getff (d); + ff =3D i8257_getff(d); if (nreg) val =3D (r->base[COUNT] << d->dshift) - r->now[COUNT]; else @@ -176,8 +176,8 @@ static uint64_t read_chan(void *opaque, hwaddr nport,= unsigned size) return (val >> (d->dshift + (ff << 3))) & 0xff; } =20 -static void write_chan(void *opaque, hwaddr nport, uint64_t data, - unsigned size) +static void i8257_write_chan(void *opaque, hwaddr nport, uint64_t data, + unsigned int size) { I8257State *d =3D opaque; int iport, ichan, nreg; @@ -187,16 +187,16 @@ static void write_chan(void *opaque, hwaddr nport, = uint64_t data, ichan =3D iport >> 1; nreg =3D iport & 1; r =3D d->regs + ichan; - if (getff (d)) { + if (i8257_getff(d)) { r->base[nreg] =3D (r->base[nreg] & 0xff) | ((data << 8) & 0xff00= ); - init_chan (d, ichan); + i8257_init_chan(d, ichan); } else { r->base[nreg] =3D (r->base[nreg] & 0xff00) | (data & 0xff); } } =20 -static void write_cont(void *opaque, hwaddr nport, uint64_t data, - unsigned size) +static void i8257_write_cont(void *opaque, hwaddr nport, uint64_t data, + unsigned int size) { I8257State *d =3D opaque; int iport, ichan =3D 0; @@ -220,7 +220,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, d->status &=3D ~(1 << (ichan + 4)); } d->status &=3D ~(1 << ichan); - DMA_run(); + i8257_dma_run(); break; =20 case 0x02: /* single mask */ @@ -228,7 +228,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, d->mask |=3D 1 << (data & 3); else d->mask &=3D ~(1 << (data & 3)); - DMA_run(); + i8257_dma_run(); break; =20 case 0x03: /* mode */ @@ -263,12 +263,12 @@ static void write_cont(void *opaque, hwaddr nport, = uint64_t data, =20 case 0x06: /* clear mask for all channels */ d->mask =3D 0; - DMA_run(); + i8257_dma_run(); break; =20 case 0x07: /* write mask for all channels */ d->mask =3D data; - DMA_run(); + i8257_dma_run(); break; =20 default: @@ -284,7 +284,7 @@ static void write_cont(void *opaque, hwaddr nport, ui= nt64_t data, #endif } =20 -static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) +static uint64_t i8257_read_cont(void *opaque, hwaddr nport, unsigned siz= e) { I8257State *d =3D opaque; int iport, val; @@ -320,7 +320,7 @@ void DMA_hold_DREQ (int nchan) ichan =3D nchan & 3; linfo ("held cont=3D%d chan=3D%d\n", ncont, ichan); dma_controllers[ncont].status |=3D 1 << (ichan + 4); - DMA_run(); + i8257_dma_run(); } =20 void DMA_release_DREQ (int nchan) @@ -331,10 +331,10 @@ void DMA_release_DREQ (int nchan) ichan =3D nchan & 3; linfo ("released cont=3D%d chan=3D%d\n", ncont, ichan); dma_controllers[ncont].status &=3D ~(1 << (ichan + 4)); - DMA_run(); + i8257_dma_run(); } =20 -static void channel_run (int ncont, int ichan) +static void i8257_channel_run(int ncont, int ichan) { int n; struct dma_regs *r =3D &dma_controllers[ncont].regs[ichan]; @@ -361,7 +361,7 @@ static void channel_run (int ncont, int ichan) static QEMUBH *dma_bh; static bool dma_bh_scheduled; =20 -static void DMA_run (void) +static void i8257_dma_run(void) { I8257State *d; int icont, ichan; @@ -384,7 +384,7 @@ static void DMA_run (void) mask =3D 1 << ichan; =20 if ((0 =3D=3D (d->mask & mask)) && (0 !=3D (d->status & (mas= k << 4)))) { - channel_run (icont, ichan); + i8257_channel_run(icont, ichan); rearm =3D 1; } } @@ -398,10 +398,10 @@ out: } } =20 -static void DMA_run_bh(void *unused) +static void i8257_dma_run_bh(void *unused) { dma_bh_scheduled =3D false; - DMA_run(); + i8257_dma_run(); } =20 void DMA_register_channel (int nchan, @@ -473,13 +473,14 @@ void DMA_schedule(void) } } =20 -static void dma_reset(void *opaque) +static void i8257_reset(void *opaque) { I8257State *d =3D opaque; - write_cont(d, (0x05 << d->dshift), 0, 1); + i8257_write_cont(d, (0x05 << d->dshift), 0, 1); } =20 -static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int = dma_len) +static int i8257_phony_handler(void *opaque, int nchan, int dma_pos, + int dma_len) { trace_i8257_unregistered_dma(nchan, dma_pos, dma_len); return dma_pos; @@ -487,8 +488,8 @@ static int dma_phony_handler (void *opaque, int nchan= , int dma_pos, int dma_len) =20 =20 static const MemoryRegionOps channel_io_ops =3D { - .read =3D read_chan, - .write =3D write_chan, + .read =3D i8257_read_chan, + .write =3D i8257_write_chan, .endianness =3D DEVICE_NATIVE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -498,21 +499,21 @@ static const MemoryRegionOps channel_io_ops =3D { =20 /* IOport from page_base */ static const MemoryRegionPortio page_portio_list[] =3D { - { 0x01, 3, 1, .write =3D write_page, .read =3D read_page, }, - { 0x07, 1, 1, .write =3D write_page, .read =3D read_page, }, + { 0x01, 3, 1, .write =3D i8257_write_page, .read =3D i8257_read_page= , }, + { 0x07, 1, 1, .write =3D i8257_write_page, .read =3D i8257_read_page= , }, PORTIO_END_OF_LIST(), }; =20 /* IOport from pageh_base */ static const MemoryRegionPortio pageh_portio_list[] =3D { - { 0x01, 3, 1, .write =3D write_pageh, .read =3D read_pageh, }, - { 0x07, 3, 1, .write =3D write_pageh, .read =3D read_pageh, }, + { 0x01, 3, 1, .write =3D i8257_write_pageh, .read =3D i8257_read_pag= eh, }, + { 0x07, 3, 1, .write =3D i8257_write_pageh, .read =3D i8257_read_pag= eh, }, PORTIO_END_OF_LIST(), }; =20 static const MemoryRegionOps cont_io_ops =3D { - .read =3D read_cont, - .write =3D write_cont, + .read =3D i8257_read_cont, + .write =3D i8257_write_cont, .endianness =3D DEVICE_NATIVE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -545,10 +546,10 @@ static void dma_init2(I8257State *d, int base, int = dshift, memory_region_add_subregion(isa_address_space_io(NULL), base + (8 << d->dshift), &d->cont_io); =20 - qemu_register_reset(dma_reset, d); - dma_reset(d); + qemu_register_reset(i8257_reset, d); + i8257_reset(d); for (i =3D 0; i < ARRAY_SIZE (d->regs); ++i) { - d->regs[i].transfer_handler =3D dma_phony_handler; + d->regs[i].transfer_handler =3D i8257_phony_handler; } } =20 @@ -568,9 +569,9 @@ static const VMStateDescription vmstate_dma_regs =3D = { } }; =20 -static int dma_post_load(void *opaque, int version_id) +static int i8257_post_load(void *opaque, int version_id) { - DMA_run(); + i8257_dma_run(); =20 return 0; } @@ -579,7 +580,7 @@ static const VMStateDescription vmstate_dma =3D { .name =3D "dma", .version_id =3D 1, .minimum_version_id =3D 1, - .post_load =3D dma_post_load, + .post_load =3D i8257_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT8(command, I8257State), VMSTATE_UINT8(mask, I8257State), @@ -598,5 +599,5 @@ void DMA_init(ISABus *bus, int high_page_enable) vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); =20 - dma_bh =3D qemu_bh_new(DMA_run_bh, NULL); + dma_bh =3D qemu_bh_new(i8257_dma_run_bh, NULL); } --=20 2.1.4