From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57946) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aDpHn-0003B4-LQ for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aDpHk-0001cC-5u for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:39 -0500 Received: from smtp5-g21.free.fr ([212.27.42.5]:17922) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aDpHj-0001bh-SP for qemu-devel@nongnu.org; Tue, 29 Dec 2015 03:05:36 -0500 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Tue, 29 Dec 2015 09:04:44 +0100 Message-Id: <1451376295-28834-8-git-send-email-hpoussin@reactos.org> In-Reply-To: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> References: <1451376295-28834-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 07/17] i8257: QOM'ify List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , "Michael S. Tsirkin" Signed-off-by: Herv=C3=A9 Poussineau --- hw/dma/i8257.c | 160 ++++++++++++++++++++++++++++++++++++++-------------= ------ 1 file changed, 107 insertions(+), 53 deletions(-) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index 03d27de..20231d6 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -26,6 +26,10 @@ #include "qemu/main-loop.h" #include "trace.h" =20 +#define TYPE_I8257 "i8257" +#define I8257(obj) \ + OBJECT_CHECK(I8257State, (obj), TYPE_I8257) + /* #define DEBUG_DMA */ =20 #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__) @@ -53,11 +57,17 @@ struct dma_regs { #define COUNT 1 =20 typedef struct I8257State { + ISADevice parent_obj; + + int32_t base; + int32_t page_base; + int32_t pageh_base; + int32_t dshift; + uint8_t status; uint8_t command; uint8_t mask; uint8_t flip_flop; - int dshift; struct dma_regs regs[4]; MemoryRegion channel_io; MemoryRegion cont_io; @@ -67,7 +77,7 @@ typedef struct I8257State { int running; } I8257State; =20 -static I8257State dma_controllers[2]; +static I8257State *dma_controllers[2]; =20 enum { CMD_MEMORY_TO_MEMORY =3D 0x01, @@ -313,7 +323,7 @@ static uint64_t i8257_read_cont(void *opaque, hwaddr = nport, unsigned size) =20 int DMA_get_channel_mode (int nchan) { - return dma_controllers[nchan > 3].regs[nchan & 3].mode; + return dma_controllers[nchan > 3]->regs[nchan & 3].mode; } =20 void DMA_hold_DREQ (int nchan) @@ -323,8 +333,8 @@ void DMA_hold_DREQ (int nchan) ncont =3D nchan > 3; ichan =3D nchan & 3; linfo ("held cont=3D%d chan=3D%d\n", ncont, ichan); - dma_controllers[ncont].status |=3D 1 << (ichan + 4); - i8257_dma_run(&dma_controllers[ncont]); + dma_controllers[ncont]->status |=3D 1 << (ichan + 4); + i8257_dma_run(dma_controllers[ncont]); } =20 void DMA_release_DREQ (int nchan) @@ -334,8 +344,8 @@ void DMA_release_DREQ (int nchan) ncont =3D nchan > 3; ichan =3D nchan & 3; linfo ("released cont=3D%d chan=3D%d\n", ncont, ichan); - dma_controllers[ncont].status &=3D ~(1 << (ichan + 4)); - i8257_dma_run(&dma_controllers[ncont]); + dma_controllers[ncont]->status &=3D ~(1 << (ichan + 4)); + i8257_dma_run(dma_controllers[ncont]); } =20 static void i8257_channel_run(I8257State *d, int ichan) @@ -405,14 +415,14 @@ void DMA_register_channel (int nchan, ncont =3D nchan > 3; ichan =3D nchan & 3; =20 - r =3D dma_controllers[ncont].regs + ichan; + r =3D dma_controllers[ncont]->regs + ichan; r->transfer_handler =3D transfer_handler; r->opaque =3D opaque; } =20 int DMA_read_memory (int nchan, void *buf, int pos, int len) { - struct dma_regs *r =3D &dma_controllers[nchan > 3].regs[nchan & 3]; + struct dma_regs *r =3D &dma_controllers[nchan > 3]->regs[nchan & 3]; hwaddr addr =3D ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now= [ADDR]; =20 if (r->mode & 0x20) { @@ -434,7 +444,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, i= nt len) =20 int DMA_write_memory (int nchan, void *buf, int pos, int len) { - struct dma_regs *r =3D &dma_controllers[nchan > 3].regs[nchan & 3]; + struct dma_regs *r =3D &dma_controllers[nchan > 3]->regs[nchan & 3]; hwaddr addr =3D ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now= [ADDR]; =20 if (r->mode & 0x20) { @@ -459,15 +469,15 @@ int DMA_write_memory (int nchan, void *buf, int pos= , int len) */ void DMA_schedule(void) { - if (dma_controllers[0].dma_bh_scheduled || - dma_controllers[1].dma_bh_scheduled) { + if (dma_controllers[0]->dma_bh_scheduled || + dma_controllers[1]->dma_bh_scheduled) { qemu_notify_event(); } } =20 -static void i8257_reset(void *opaque) +static void i8257_reset(DeviceState *dev) { - I8257State *d =3D opaque; + I8257State *d =3D I8257(dev); i8257_write_cont(d, (0x05 << d->dshift), 0, 1); } =20 @@ -513,40 +523,6 @@ static const MemoryRegionOps cont_io_ops =3D { }, }; =20 -/* dshift =3D 0: 8 bit DMA, 1 =3D 16 bit DMA */ -static void dma_init2(I8257State *d, int base, int dshift, - int page_base, int pageh_base) -{ - int i; - - d->dshift =3D dshift; - - memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d, - "dma-chan", 8 << d->dshift); - memory_region_add_subregion(isa_address_space_io(NULL), - base, &d->channel_io); - - isa_register_portio_list(NULL, page_base, page_portio_list, d, - "dma-page"); - if (pageh_base >=3D 0) { - isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d, - "dma-pageh"); - } - - memory_region_init_io(&d->cont_io, NULL, &cont_io_ops, d, "dma-cont"= , - 8 << d->dshift); - memory_region_add_subregion(isa_address_space_io(NULL), - base + (8 << d->dshift), &d->cont_io); - - qemu_register_reset(i8257_reset, d); - i8257_reset(d); - for (i =3D 0; i < ARRAY_SIZE (d->regs); ++i) { - d->regs[i].transfer_handler =3D i8257_phony_handler; - } - - d->dma_bh =3D qemu_bh_new(i8257_dma_run, d); -} - static const VMStateDescription vmstate_dma_regs =3D { .name =3D "dma_regs", .version_id =3D 1, @@ -571,7 +547,7 @@ static int i8257_post_load(void *opaque, int version_= id) return 0; } =20 -static const VMStateDescription vmstate_dma =3D { +static const VMStateDescription vmstate_i8257 =3D { .name =3D "dma", .version_id =3D 1, .minimum_version_id =3D 1, @@ -587,10 +563,88 @@ static const VMStateDescription vmstate_dma =3D { } }; =20 +static void i8257_realize(DeviceState *dev, Error **errp) +{ + ISADevice *isa =3D ISA_DEVICE(dev); + I8257State *d =3D I8257(dev); + int i; + + memory_region_init_io(&d->channel_io, NULL, &channel_io_ops, d, + "dma-chan", 8 << d->dshift); + memory_region_add_subregion(isa_address_space_io(isa), + d->base, &d->channel_io); + + isa_register_portio_list(isa, d->page_base, page_portio_list, d, + "dma-page"); + if (d->pageh_base >=3D 0) { + isa_register_portio_list(isa, d->pageh_base, pageh_portio_list, = d, + "dma-pageh"); + } + + memory_region_init_io(&d->cont_io, OBJECT(isa), &cont_io_ops, d, + "dma-cont", 8 << d->dshift); + memory_region_add_subregion(isa_address_space_io(isa), + d->base + (8 << d->dshift), &d->cont_io)= ; + + for (i =3D 0; i < ARRAY_SIZE(d->regs); ++i) { + d->regs[i].transfer_handler =3D i8257_phony_handler; + } + + d->dma_bh =3D qemu_bh_new(i8257_dma_run, d); +} + +static Property i8257_properties[] =3D { + DEFINE_PROP_INT32("base", I8257State, base, 0x00), + DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80), + DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480), + DEFINE_PROP_INT32("dshift", I8257State, dshift, 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void i8257_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D i8257_realize; + dc->reset =3D i8257_reset; + dc->vmsd =3D &vmstate_i8257; + dc->props =3D i8257_properties; +} + +static const TypeInfo i8257_info =3D { + .name =3D TYPE_I8257, + .parent =3D TYPE_ISA_DEVICE, + .instance_size =3D sizeof(I8257State), + .class_init =3D i8257_class_init, +}; + +static void i8257_register_types(void) +{ + type_register_static(&i8257_info); +} + +type_init(i8257_register_types) + void DMA_init(ISABus *bus, int high_page_enable) { - dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x4= 80 : -1); - dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x4= 88 : -1); - vmstate_register (NULL, 0, &vmstate_dma, &dma_controllers[0]); - vmstate_register (NULL, 1, &vmstate_dma, &dma_controllers[1]); + ISADevice *isa1, *isa2; + DeviceState *d; + + isa1 =3D isa_create(bus, TYPE_I8257); + d =3D DEVICE(isa1); + qdev_prop_set_int32(d, "base", 0x00); + qdev_prop_set_int32(d, "page-base", 0x80); + qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x480 : -1); + qdev_prop_set_int32(d, "dshift", 0); + qdev_init_nofail(d); + dma_controllers[0] =3D I8257(d); + + isa2 =3D isa_create(bus, TYPE_I8257); + d =3D DEVICE(isa2); + qdev_prop_set_int32(d, "base", 0xc0); + qdev_prop_set_int32(d, "page-base", 0x88); + qdev_prop_set_int32(d, "pageh-base", high_page_enable ? 0x488 : -1); + qdev_prop_set_int32(d, "dshift", 1); + qdev_init_nofail(d); + dma_controllers[1] =3D I8257(d); } --=20 2.1.4