From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32768) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8n4f-0001vG-6p for qemu-devel@nongnu.org; Tue, 15 Dec 2015 05:43:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1a8n4b-0007ka-Vu for qemu-devel@nongnu.org; Tue, 15 Dec 2015 05:43:17 -0500 Received: from mx5-phx2.redhat.com ([209.132.183.37]:33959) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1a8n4b-0007kV-NZ for qemu-devel@nongnu.org; Tue, 15 Dec 2015 05:43:13 -0500 Date: Tue, 15 Dec 2015 05:43:06 -0500 (EST) From: Paolo Bonzini Message-ID: <145192308.40660604.1450176186593.JavaMail.zimbra@redhat.com> In-Reply-To: <33183CC9F5247A488A2544077AF19020B02B4BE3@SZXEMA503-MBS.china.huawei.com> References: <1449926146-14828-1-git-send-email-arei.gonglei@huawei.com> <566E9259.2010404@redhat.com> <33183CC9F5247A488A2544077AF19020B02B4533@SZXEMA503-MBS.china.huawei.com> <566EBB34.5030205@redhat.com> <33183CC9F5247A488A2544077AF19020B02B45BB@SZXEMA503-MBS.china.huawei.com> <566EC61A.7090407@redhat.com> <33183CC9F5247A488A2544077AF19020B02B4BE3@SZXEMA503-MBS.china.huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] rtc: introduce nmi disable bit handler for cmos List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Gonglei (Arei)" , Radim Krcmar Cc: "Huangpeng (Peter)" , kevin@koconnor.net, qemu-devel@nongnu.org, ehabkost@redhat.com, rth@twiddle.net > Hi Paolo, >=20 > /* for KVM_GET/SET_VCPU_EVENTS */ > struct kvm_vcpu_events { > ... > struct { > =09=09__u8 injected; > =09=09__u8 pending; > =09=09__u8 masked; > =09=09__u8 pad; > =09} nmi; > ... >=20 > I found that the nmi.masked property does these enable or disable NMI job= s. > So, I think we don't need to add a new bit. Right? nmi.masked says whether the CPU is accepting the NMIs, and is cleared by the next IRET instruction. This is a different thing; it probably shouldn't affect NMI IPIs, and it definitely should remain set until cleared via the RTC. So it should be something like _u8 external_nmi_disabled; or similar. *However* I found this in the ICH9 datasheet: The ICH9's I/O APIC can only send interrupts due to interrupts which do not include SMI, NMI or INIT. This means that in IA-32/Intel =C2=AE = 64 based platforms, Front Side Bus interrupt message format delivery modes 010 (SMI/PMI), 100 (NMI), and 101 (INIT) as indicated in this section, must not be used and is not supported. In theory the PIIX4 could deliver such messages, but perhaps we could disable them in the KVM IOAPIC. If we do this, there is no need for a change to struct kvm_vcpu_events, because all external NMI sources will be in userspace. Radim, what do you think? Paolo