From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57589) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHXuj-0007gJ-IS for qemu-devel@nongnu.org; Fri, 08 Jan 2016 09:21:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aHXuf-0003sU-KP for qemu-devel@nongnu.org; Fri, 08 Jan 2016 09:21:13 -0500 Received: from mx1.redhat.com ([209.132.183.28]:58655) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aHXuf-0003sN-Ep for qemu-devel@nongnu.org; Fri, 08 Jan 2016 09:21:09 -0500 Date: Fri, 8 Jan 2016 16:21:05 +0200 From: "Michael S. Tsirkin" Message-ID: <1452262668-31244-52-git-send-email-mst@redhat.com> References: <1452262668-31244-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1452262668-31244-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PULL 51/59] pc: acpi: q35: move PCI0 device definition into SSDT List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , Richard Henderson , Paolo Bonzini , Eduardo Habkost , Igor Mammedov From: Igor Mammedov Signed-off-by: Igor Mammedov Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/acpi-build.c | 14 +++++++++----- hw/i386/q35-acpi-dsdt.dsl | 13 ------------- 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 29abb99..609baf4 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1983,11 +1983,15 @@ build_ssdt(GArray *table_data, GArray *linker, build_piix4_pci0_int(ssdt); } else { sb_scope = aml_scope("_SB"); - scope = aml_scope("PCI0"); - aml_append(scope, aml_name_decl("SUPP", aml_int(0))); - aml_append(scope, aml_name_decl("CTRL", aml_int(0))); - aml_append(scope, build_q35_osc_method()); - aml_append(sb_scope, scope); + dev = aml_device("PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(1))); + aml_append(dev, aml_name_decl("SUPP", aml_int(0))); + aml_append(dev, aml_name_decl("CTRL", aml_int(0))); + aml_append(dev, build_q35_osc_method()); + aml_append(sb_scope, dev); aml_append(ssdt, sb_scope); build_hpet_aml(ssdt); diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl index b53663c..f234f5c 100644 --- a/hw/i386/q35-acpi-dsdt.dsl +++ b/hw/i386/q35-acpi-dsdt.dsl @@ -42,17 +42,4 @@ DefinitionBlock ( PCIB, 8, } } - - -/**************************************************************** - * PCI Bus definition - ****************************************************************/ - Scope(\_SB) { - Device(PCI0) { - Name(_HID, EisaId("PNP0A08")) - Name(_CID, EisaId("PNP0A03")) - Name(_ADR, 0x00) - Name(_UID, 1) - } - } } -- MST