[Qemu-devel] [V3 0/4] AMD IOMMU

[David Kiarie <davidkiarie4@gmail.com>]

David Kiarie (4):
  hw/core: Add AMD IO MMU to machine properties
  hw/i386: ACPI table for AMD IO MMU
  hw/pci-host: Emulate AMD IO MMU

 hw/core/machine.c           |   17 +-
 hw/i386/Makefile.objs       |    1 +
 hw/i386/acpi-build.c        |   96 +++
 hw/i386/amd_iommu.c         | 1420 +++++++++++++++++++++++++++++++++++++++++++
 hw/i386/amd_iommu.h         |  399 ++++++++++++
 hw/pci-host/piix.c          |   11 +
 hw/pci-host/q35.c           |   16 +-
 include/hw/acpi/acpi-defs.h |   55 ++
 include/hw/boards.h         |    3 +-
 include/hw/pci/pci.h        |    2 +
 qemu-options.hx             |    6 +-
 util/qemu-config.c          |    4 +-
 12 files changed, 2014 insertions(+), 16 deletions(-)
 create mode 100644 hw/i386/amd_iommu.c
 create mode 100644 hw/i386/amd_iommu.h

Hello,

This series introduces AMD IO MMU emulation to qemu. It's the third version.

Changes since v2.
  -Coding style; fixed all errors reported by scripts/checkpatch.pl as suggested by Micheal
  -Implemented read/only and write 1/clear registers to IO MMU MMIO 
  -Cleaned up dead code
  -Introduced a switch that controls IO MMU emulation and what type is emulated i.e 
            q35,iommu=amd|intel
   as suggested by Marcel
  -Tested with audio device passthrough (ac97 with sound driver alsa)
  -Reserved memory for IO MMU MMIO via ACPI (I need someone to check this)

I was supposed to implement interrupts related to w1/c registers but I decided to reserve everything to do with interrupts for later

Testing procedure outlined here 
   http://www.linux-kvm.org/page/How_to_assign_devices_with_VT-d_in_KVM
-- 
2.1.4