From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aJijT-0002Yu-MX for qemu-devel@nongnu.org; Thu, 14 Jan 2016 09:18:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aJijS-0003Jx-Q4 for qemu-devel@nongnu.org; Thu, 14 Jan 2016 09:18:35 -0500 From: Peter Maydell Date: Thu, 14 Jan 2016 13:52:52 +0000 Message-Id: <1452779575-32582-17-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1452779575-32582-1-git-send-email-peter.maydell@linaro.org> References: <1452779575-32582-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v3 16/19] target-arm: Support multiple address spaces in page table walks List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-arm@nongnu.org, "Edgar E. Iglesias" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Andreas=20F=C3=A4rber?= If we have a secure address space, use it in page table walks: when doing the physical accesses to read descriptors, make them through the correct address space. (The descriptor reads are the only direct physical accesses made in target-arm/ for CPUs which might have TrustZone.) Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias --- target-arm/cpu.h | 9 +++++++++ target-arm/helper.c | 8 ++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ee873b7..5f81342 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -2003,6 +2003,15 @@ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs) { return attrs.secure ? ARMASIdx_S : ARMASIdx_NS; } + +/* Return the AddressSpace to use for a memory access + * (which depends on whether the access is S or NS, and whether + * the board gave us a separate AddressSpace for S accesses). + */ +static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs) +{ + return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs)); +} #endif #endif diff --git a/target-arm/helper.c b/target-arm/helper.c index 26cd74b..a06bfaf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -6268,13 +6268,15 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; MemTxAttrs attrs = {}; + AddressSpace *as; attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); if (fi->s1ptw) { return 0; } - return address_space_ldl(cs->as, addr, attrs, NULL); + return address_space_ldl(as, addr, attrs, NULL); } static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, @@ -6284,13 +6286,15 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; MemTxAttrs attrs = {}; + AddressSpace *as; attrs.secure = is_secure; + as = arm_addressspace(cs, attrs); addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi); if (fi->s1ptw) { return 0; } - return address_space_ldq(cs->as, addr, attrs, NULL); + return address_space_ldq(as, addr, attrs, NULL); } static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, -- 1.9.1