From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: patches@linaro.org, qemu-arm@nongnu.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Andreas Färber" <afaerber@suse.de>
Subject: [Qemu-devel] [PATCH v3 06/19] cputlb.c: Use correct address space when looking up MemoryRegionSection
Date: Thu, 14 Jan 2016 13:52:42 +0000 [thread overview]
Message-ID: <1452779575-32582-7-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1452779575-32582-1-git-send-email-peter.maydell@linaro.org>
When looking up the MemoryRegionSection for the new TLB entry in
tlb_set_page_with_attrs(), use cpu_asidx_from_attrs() to determine
the correct address space index for the lookup, and pass it into
address_space_translate_for_iotlb().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cputlb.c | 3 ++-
exec.c | 7 ++++---
include/exec/exec-all.h | 4 ++--
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index bf1d50a..f1c1082 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -356,6 +356,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
CPUTLBEntry *te;
hwaddr iotlb, xlat, sz;
unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
+ int asidx = cpu_asidx_from_attrs(cpu, attrs);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
@@ -363,7 +364,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
}
sz = size;
- section = address_space_translate_for_iotlb(cpu, paddr, &xlat, &sz);
+ section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
#if defined(DEBUG_TLB)
diff --git a/exec.c b/exec.c
index 8bc3288..884586a 100644
--- a/exec.c
+++ b/exec.c
@@ -431,12 +431,13 @@ MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
/* Called from RCU critical section */
MemoryRegionSection *
-address_space_translate_for_iotlb(CPUState *cpu, hwaddr addr,
+address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
hwaddr *xlat, hwaddr *plen)
{
MemoryRegionSection *section;
- section = address_space_translate_internal(cpu->cpu_ases[0].memory_dispatch,
- addr, xlat, plen, false);
+ AddressSpaceDispatch *d = cpu->cpu_ases[asidx].memory_dispatch;
+
+ section = address_space_translate_internal(d, addr, xlat, plen, false);
assert(!section->mr->iommu_ops);
return section;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index caa78a9..ee9757f 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -432,8 +432,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
MemoryRegionSection *
-address_space_translate_for_iotlb(CPUState *cpu, hwaddr addr, hwaddr *xlat,
- hwaddr *plen);
+address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
+ hwaddr *xlat, hwaddr *plen);
hwaddr memory_region_section_get_iotlb(CPUState *cpu,
MemoryRegionSection *section,
target_ulong vaddr,
--
1.9.1
next prev parent reply other threads:[~2016-01-14 14:17 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-14 13:52 [Qemu-devel] [PATCH v3 00/19] Add support for multiple address spaces per CPU and use it for ARM TrustZone Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 01/19] exec.c: Don't set cpu->as until cpu_address_space_init Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 02/19] exec.c: Allow target CPUs to define multiple AddressSpaces Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 03/19] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 04/19] cpu: Add new get_phys_page_attrs_debug() method Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 05/19] cpu: Add new asidx_from_attrs() method Peter Maydell
2016-01-14 13:52 ` Peter Maydell [this message]
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 07/19] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 08/19] exec.c: Add cpu_get_address_space() Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 09/19] exec.c: Use cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 10/19] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 11/19] memory: Add address_space_init_shareable() Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 12/19] qom/cpu: Add MemoryRegion property Peter Maydell
2016-01-14 23:37 ` [Qemu-devel] [Qemu-arm] " Peter Crosthwaite
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 13/19] target-arm: Add QOM property for Secure memory region Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 14/19] target-arm: Implement asidx_from_attrs Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 15/19] target-arm: Implement cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 16/19] target-arm: Support multiple address spaces in page table walks Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 17/19] hw/arm/virt: Wire up memory region to CPUs explicitly Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 18/19] hw/arm/virt: add secure memory region and UART Peter Maydell
2016-01-14 13:52 ` [Qemu-devel] [PATCH v3 19/19] HACK: rearrange the virt memory map to suit OP-TEE Peter Maydell
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