From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52157) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLZIe-0003Am-Os for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:38:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aLZIb-0001k0-16 for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:38:32 -0500 Received: from mx1.redhat.com ([209.132.183.28]:59649) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aLZIa-0001jo-R2 for qemu-devel@nongnu.org; Tue, 19 Jan 2016 11:38:28 -0500 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id 578588E757 for ; Tue, 19 Jan 2016 16:38:28 +0000 (UTC) Message-ID: <1453221507.32741.240.camel@redhat.com> From: Alex Williamson Date: Tue, 19 Jan 2016 09:38:27 -0700 In-Reply-To: <569DF9D4.3050206@gmail.com> References: <20160118230413.2140.8336.stgit@gimli.home> <569DF9D4.3050206@gmail.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RE-RESEND PATCH] pci: Adjust PCI config limit based on bus topology List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: marcel@redhat.com, mst@redhat.com Cc: qemu-devel@nongnu.org On Tue, 2016-01-19 at 10:54 +0200, Marcel Apfelbaum wrote: > On 01/19/2016 01:06 AM, Alex Williamson wrote: > > A conventional PCI bus does not support config space accesses above > > the standard 256 byte configuration space.=C2=A0=C2=A0PCIe-to-PCI bri= dges are > > not permitted to forward transactions if the extended register > > address > > field is non-zero and must handle it as an unsupported request > > (PCIe > > bridge spec rev 1.0, 4.1.3, 4.1.4).=C2=A0=C2=A0Therefore, we should n= ot > > support > > extended config space if there is a conventional bus anywhere on > > the > > path to a device. > >=20 > > Signed-off-by: Alex Williamson > > --- > > Previous postings: > > https://lists.gnu.org/archive/html/qemu-devel/2015-10/msg05384.html > > https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg02422.html > >=20 > > =C2=A0 hw/pci/pci_host.c |=C2=A0=C2=A0=C2=A026 ++++++++++++++++++++++= ++++ > > =C2=A0 1 file changed, 26 insertions(+) > >=20 > > diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c > > index 49f59a5..3a3e294 100644 > > --- a/hw/pci/pci_host.c > > +++ b/hw/pci/pci_host.c > > @@ -19,6 +19,7 @@ > > =C2=A0=C2=A0=C2=A0*/ > >=20 > > =C2=A0 #include "hw/pci/pci.h" > > +#include "hw/pci/pci_bridge.h" > > =C2=A0 #include "hw/pci/pci_host.h" > > =C2=A0 #include "hw/pci/pci_bus.h" > > =C2=A0 #include "trace.h" > > @@ -49,9 +50,29 @@ static inline PCIDevice > > *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return pci_find_device(bus, bus_n= um, devfn); > > =C2=A0 } > >=20 > > +static void pci_adjust_config_limit(PCIBus *bus, uint32_t *limit) > > +{ > > +=C2=A0=C2=A0=C2=A0=C2=A0if (*limit > PCI_CONFIG_SPACE_SIZE) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (!pci_bus_is_expr= ess(bus)) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0*limit =3D PCI_CONFIG_SPACE_SIZE; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0return; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (!pci_bus_is_root= (bus)) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0PCIDevice *bridge =3D pci_bridge_get_device(bus); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0pci_adjust_config_limit(bridge->bus, limit); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0} > > +=C2=A0=C2=A0=C2=A0=C2=A0} > > +} > > + > > =C2=A0 void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t > > addr, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0u= int32_t limit, uint32_t val, > > uint32_t len) > > =C2=A0 { > > +=C2=A0=C2=A0=C2=A0=C2=A0pci_adjust_config_limit(pci_dev->bus, &limit= ); > > +=C2=A0=C2=A0=C2=A0=C2=A0if (limit <=3D addr) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return; > > +=C2=A0=C2=A0=C2=A0=C2=A0} > > + > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0assert(len <=3D 4); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* non-zero functions are only ex= posed when function 0 is > > present, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* allowing direct removal o= f unexposed functions. > > @@ -70,6 +91,11 @@ uint32_t pci_host_config_read_common(PCIDevice > > *pci_dev, uint32_t addr, > > =C2=A0 { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0uint32_t ret; > >=20 > > +=C2=A0=C2=A0=C2=A0=C2=A0pci_adjust_config_limit(pci_dev->bus, &limit= ); > > +=C2=A0=C2=A0=C2=A0=C2=A0if (limit <=3D addr) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0return ~0x0; > > +=C2=A0=C2=A0=C2=A0=C2=A0} > > + > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0assert(len <=3D 4); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0/* non-zero functions are only ex= posed when function 0 is > > present, > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0* allowing direct removal o= f unexposed functions. > >=20 > >=20 >=20 > Quick question: could we check the limit as part of pci_config_size? If we plugin a physical PCIe card behind a bridge that masks access to the extended configuration space, does the config size for that card change? =C2=A0No, it's up to the bridge to drop the transactions, which seems like how we probably want to handle it in QEMU as well. > Anyway, it looks OK to me. >=20 > Reviewed-by: Marcel Apfelbaum Thanks, Alex