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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 11/36] cpu: Add new get_phys_page_attrs_debug() method
Date: Thu, 21 Jan 2016 14:56:04 +0000	[thread overview]
Message-ID: <1453388189-13092-12-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1453388189-13092-1-git-send-email-peter.maydell@linaro.org>

Add a new optional method get_phys_page_attrs_debug() to CPUClass.
This is like the existing get_phys_page_debug(), but also returns
the memory transaction attributes to use for the access.
This will be necessary for CPUs which have multiple address
spaces and use the attributes to select the correct address
space.

We provide a wrapper function cpu_get_phys_page_attrs_debug()
which falls back to the existing get_phys_page_debug(), so we
don't need to change every target CPU.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 include/qom/cpu.h | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index ae17932..58605a5 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -98,6 +98,10 @@ struct TranslationBlock;
  * #TranslationBlock.
  * @handle_mmu_fault: Callback for handling an MMU fault.
  * @get_phys_page_debug: Callback for obtaining a physical address.
+ * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the
+ *       associated memory transaction attributes to use for the access.
+ *       CPUs which use memory transaction attributes should implement this
+ *       instead of get_phys_page_debug.
  * @gdb_read_register: Callback for letting GDB read a register.
  * @gdb_write_register: Callback for letting GDB write a register.
  * @debug_excp_handler: Callback for handling debug exceptions.
@@ -152,6 +156,8 @@ typedef struct CPUClass {
     int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
                             int mmu_index);
     hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
+    hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr,
+                                        MemTxAttrs *attrs);
     int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
     int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
     void (*debug_excp_handler)(CPUState *cpu);
@@ -445,6 +451,32 @@ void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 
 #ifndef CONFIG_USER_ONLY
 /**
+ * cpu_get_phys_page_attrs_debug:
+ * @cpu: The CPU to obtain the physical page address for.
+ * @addr: The virtual address.
+ * @attrs: Updated on return with the memory transaction attributes to use
+ *         for this access.
+ *
+ * Obtains the physical page corresponding to a virtual one, together
+ * with the corresponding memory transaction attributes to use for the access.
+ * Use it only for debugging because no protection checks are done.
+ *
+ * Returns: Corresponding physical page address or -1 if no page found.
+ */
+static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+                                                   MemTxAttrs *attrs)
+{
+    CPUClass *cc = CPU_GET_CLASS(cpu);
+
+    if (cc->get_phys_page_attrs_debug) {
+        return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+    }
+    /* Fallback for CPUs which don't implement the _attrs_ hook */
+    *attrs = MEMTXATTRS_UNSPECIFIED;
+    return cc->get_phys_page_debug(cpu, addr);
+}
+
+/**
  * cpu_get_phys_page_debug:
  * @cpu: The CPU to obtain the physical page address for.
  * @addr: The virtual address.
@@ -456,9 +488,9 @@ void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
  */
 static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
 {
-    CPUClass *cc = CPU_GET_CLASS(cpu);
+    MemTxAttrs attrs = {};
 
-    return cc->get_phys_page_debug(cpu, addr);
+    return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
 }
 #endif
 
-- 
1.9.1

  parent reply	other threads:[~2016-01-21 14:56 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-01-21 14:55 [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 01/36] qdev: get_child_bus(): Use QOM lookup if available Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 02/36] m25p80.c: Add sst25wf080 SPI flash device Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 03/36] ssi: Move ssi.h into a separate directory Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 04/36] xilinx_spips: Separate the state struct into a header Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 05/36] xlnx-zynqmp: Connect the SPI devices Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 06/36] xlnx-ep108: Connect the SPI Flash Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 07/36] misc: zynq-xadc: Fix off-by-one Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 09/36] exec.c: Allow target CPUs to define multiple AddressSpaces Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page Peter Maydell
2016-01-21 14:56 ` Peter Maydell [this message]
2016-01-21 14:56 ` [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 13/36] cputlb.c: Use correct address space when looking up MemoryRegionSection Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 14/36] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 15/36] exec.c: Add cpu_get_address_space() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 17/36] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 19/36] qom/cpu: Add MemoryRegion property Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 21/36] target-arm: Implement asidx_from_attrs Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 22/36] target-arm: Implement cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 25/36] hw/arm/virt: add secure memory region and UART Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 30/36] target-arm: Use a single entry point for AArch64 and AArch32 exceptions Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32 Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return event checks Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 35/36] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register Peter Maydell
2016-01-21 15:53 ` [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell

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