From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PULL 13/36] cputlb.c: Use correct address space when looking up MemoryRegionSection
Date: Thu, 21 Jan 2016 14:56:06 +0000 [thread overview]
Message-ID: <1453388189-13092-14-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1453388189-13092-1-git-send-email-peter.maydell@linaro.org>
When looking up the MemoryRegionSection for the new TLB entry in
tlb_set_page_with_attrs(), use cpu_asidx_from_attrs() to determine
the correct address space index for the lookup, and pass it into
address_space_translate_for_iotlb().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
cputlb.c | 3 ++-
exec.c | 7 ++++---
include/exec/exec-all.h | 4 ++--
3 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index bf1d50a..f1c1082 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -356,6 +356,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
CPUTLBEntry *te;
hwaddr iotlb, xlat, sz;
unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE;
+ int asidx = cpu_asidx_from_attrs(cpu, attrs);
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
@@ -363,7 +364,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
}
sz = size;
- section = address_space_translate_for_iotlb(cpu, paddr, &xlat, &sz);
+ section = address_space_translate_for_iotlb(cpu, asidx, paddr, &xlat, &sz);
assert(sz >= TARGET_PAGE_SIZE);
#if defined(DEBUG_TLB)
diff --git a/exec.c b/exec.c
index 8bc3288..884586a 100644
--- a/exec.c
+++ b/exec.c
@@ -431,12 +431,13 @@ MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr,
/* Called from RCU critical section */
MemoryRegionSection *
-address_space_translate_for_iotlb(CPUState *cpu, hwaddr addr,
+address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
hwaddr *xlat, hwaddr *plen)
{
MemoryRegionSection *section;
- section = address_space_translate_internal(cpu->cpu_ases[0].memory_dispatch,
- addr, xlat, plen, false);
+ AddressSpaceDispatch *d = cpu->cpu_ases[asidx].memory_dispatch;
+
+ section = address_space_translate_internal(d, addr, xlat, plen, false);
assert(!section->mr->iommu_ops);
return section;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index caa78a9..ee9757f 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -432,8 +432,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
MemoryRegionSection *
-address_space_translate_for_iotlb(CPUState *cpu, hwaddr addr, hwaddr *xlat,
- hwaddr *plen);
+address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr,
+ hwaddr *xlat, hwaddr *plen);
hwaddr memory_region_section_get_iotlb(CPUState *cpu,
MemoryRegionSection *section,
target_ulong vaddr,
--
1.9.1
next prev parent reply other threads:[~2016-01-21 14:56 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-21 14:55 [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 01/36] qdev: get_child_bus(): Use QOM lookup if available Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 02/36] m25p80.c: Add sst25wf080 SPI flash device Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 03/36] ssi: Move ssi.h into a separate directory Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 04/36] xilinx_spips: Separate the state struct into a header Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 05/36] xlnx-zynqmp: Connect the SPI devices Peter Maydell
2016-01-21 14:55 ` [Qemu-devel] [PULL 06/36] xlnx-ep108: Connect the SPI Flash Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 07/36] misc: zynq-xadc: Fix off-by-one Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 08/36] exec.c: Don't set cpu->as until cpu_address_space_init Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 09/36] exec.c: Allow target CPUs to define multiple AddressSpaces Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 10/36] exec-all.h: Document tlb_set_page_with_attrs, tlb_set_page Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 11/36] cpu: Add new get_phys_page_attrs_debug() method Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 12/36] cpu: Add new asidx_from_attrs() method Peter Maydell
2016-01-21 14:56 ` Peter Maydell [this message]
2016-01-21 14:56 ` [Qemu-devel] [PULL 14/36] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 15/36] exec.c: Add cpu_get_address_space() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 16/36] exec.c: Use cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 17/36] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 18/36] memory: Add address_space_init_shareable() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 19/36] qom/cpu: Add MemoryRegion property Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 20/36] target-arm: Add QOM property for Secure memory region Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 21/36] target-arm: Implement asidx_from_attrs Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 22/36] target-arm: Implement cpu_get_phys_page_attrs_debug Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 23/36] target-arm: Support multiple address spaces in page table walks Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 24/36] hw/arm/virt: Wire up memory region to CPUs explicitly Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 25/36] hw/arm/virt: add secure memory region and UART Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 26/36] hw/arm/virt: Add always-on property to the virt board timer Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 27/36] arm_gic: Update ID registers based on revision Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 28/36] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 29/36] target-arm: Move aarch64_cpu_do_interrupt() to helper.c Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 30/36] target-arm: Use a single entry point for AArch64 and AArch32 exceptions Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 31/36] target-arm: Pull semihosting handling out to arm_cpu_do_interrupt() Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 32/36] target-arm: Fix wrong AArch64 entry offset for EL2/EL3 target Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 33/36] target-arm: Handle exception return from AArch64 to non-EL0 AArch32 Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 34/36] target-arm: Implement remaining illegal return event checks Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 35/36] target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode Peter Maydell
2016-01-21 14:56 ` [Qemu-devel] [PULL 36/36] target-arm: Implement FPEXC32_EL2 system register Peter Maydell
2016-01-21 15:53 ` [Qemu-devel] [PULL 00/36] target-arm queue Peter Maydell
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